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Pull requests: HexRaysSA/rax
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fix(riscv): make mstatus.SD a read-only dirty aggregate
#316
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): implement scounteren and gate U-mode counter reads
#315
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): mask mcounteren to 32 bits and gate counter reads
#314
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): make sip.SSIP software-writable regardless of mideleg
#313
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): canonicalize reserved WARL encodings in four CSRs
#312
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): trap on instruction fetch at misaligned PC without C
#306
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): use index EEW for indexed segment field spacing
#305
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): decode HLVX.WU on RV32 with H extension
#304
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): decode Zfa fmvh.x.d/fmvp.d.x on RV32 with D
#303
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv): trap on machine-level CSR accesses from U-mode
#302
opened Aug 14, 2026 by
carlosqwqqwq
Contributor
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fix(riscv,x86_64): validate vector semantics and native replay
#296
opened Aug 13, 2026 by
19h
Member
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