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mstatus.SD is stored as a writable bit instead of a read-only aggregate

Status: Open.

#311 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

scounteren is missing and U-mode counter reads ignore it

Status: Open.

#310 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

mcounteren is not masked to 32 bits and does not gate S/U-mode counter reads

Status: Open.

#309 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

sip.SSIP writes are silently dropped when mideleg is 0

Status: Open.

#308 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

Reserved encodings of four WARL CSRs are stored instead of canonicalized

Status: Open.

#307 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

Instruction fetch at a misaligned PC does not trap without the C extension

Status: Open.

#301 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

Indexed segment load/store field spacing uses SEW instead of the index EEW

Status: Open.

#300 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

HLVX.WU is rejected as illegal on RV32 with the H extension

Status: Open.

#299 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

fmvh.x.d and fmvp.d.x are rejected as illegal on RV32 with Zfa

Status: Open.

#298 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

machine-level CSR accesses from U-mode are accepted

Status: Open.

#297 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 14, 2026

wfi does not take the trap when an enabled interrupt is pending

Status: Open.

#290 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 13, 2026

sret/uret are executed via the mret path, corrupting S and M status state

Status: Open.

#289 In HexRaysSA/rax;

· carlosqwqqwq opened on Aug 13, 2026