fix(riscv): mask mcounteren to 32 bits and gate counter reads

[carlosqwqqwq]

Summary

mcounteren is a 32-bit register and counter reads in S/U-mode must be gated on it: with CY clear, a non-M read of cycle must raise an illegal-instruction exception. RAX stored mcounteren without a width mask and never gated cycle/time/instret reads, so disabled counters silently succeeded.

This change masks mcounteren writes to 32 bits and gates non-M counter reads on the corresponding enable bits.

Validation

• New regression test mcounteren_is_32bit_and_gates_counter_reads: bit 33 is not stored, U-mode reads of disabled counters trap, enabled reads succeed, and M-mode reads are unaffected.
• cargo test --lib targeted test passes; full suite shows no regressions.

Closes #309

[19h]

Thank you for the report and implementation proposal. I independently reproduced and validated the accepted behavior, then reimplemented it with direct and SMIR/JIT coverage in #296 at commit 9027ae1. No contributor patch was imported; the consolidation commit records @carlosqwqqwq as co-author. I am closing this implementation PR because it is now consolidated into #296. Please review the rollup there.