fix(riscv): trap on instruction fetch at misaligned PC without C

[carlosqwqqwq]

Summary

Fetch at a misaligned PC must raise an instruction-address-misaligned exception. RAX's fetch path has no IALIGN check, so with the C extension disabled a fetch at an odd PC reads a 16-bit compressed parcel and executes it. This change adds the alignment trap before decode (no trap when aligned; legal halfword fetch with C is preserved).

Validation

• New regression test fetch_pc_alignment_traps_without_compressed_extension: PCs 0x1001/0x1002 with isa.c=false trap with cause INSTR_MISALIGNED, mepc reads back aligned (WARL), mtval keeps the exact PC, and an aligned PC executes normally.
• New regression test fetch_pc_alignment_allows_halfwords_with_compressed_extension: with C, halfword-aligned PCs fetch a 16-bit parcel (c.nop) and advance by 2.
• cargo test --lib targeted tests pass; full suite shows no regressions.

Closes #301

[19h]

Thank you for the report and implementation proposal. I independently reproduced and validated the accepted behavior, then reimplemented it with direct and SMIR/JIT coverage in #296 at commit 9027ae1. No contributor patch was imported; the consolidation commit records @carlosqwqqwq as co-author. I am closing this implementation PR because it is now consolidated into #296. Please review the rollup there.