fix(riscv): trap on machine-level CSR accesses from U-mode

[carlosqwqqwq]

Summary

The RISC-V privileged spec encodes the minimum privilege for a CSR in the two high bits of its address; machine-level CSRs (bits 9:8 = 0b11) must raise an illegal-instruction exception when accessed from U-mode. RAX's exec_csr (src/isa/riscv/cpu/csr_ops.rs) had no privilege check, so U-mode csrrw mtvec / csrrs misa / csrr mhartid were silently accepted.

This change adds a U-mode gate at the top of exec_csr for machine-level CSR addresses. U-level and supervisor-level CSR accesses are unchanged.

Validation

• cargo test --lib: the targeted U-mode CSR-access tests pass, and the full library test suite passes with no regressions;
• QEMU 8.2.2 -cpu max reference shows SIGILL (132) for the same encodings in U-mode.
• fix is source-only; no change to U/S-level CSR semantics.

Closes #297

[19h]

Thank you for the report and implementation proposal. I independently reproduced and validated the accepted behavior, then reimplemented it with direct and SMIR/JIT coverage in #296 at commit 9027ae1. No contributor patch was imported; the consolidation commit records @carlosqwqqwq as co-author. I am closing this implementation PR because it is now consolidated into #296. Please review the rollup there.