fix(riscv): require aligned register groups for vsaddu/vsadd/vssubu/vssub

[carlosqwqqwq]

Closes #279

Summary

The saturating add/subtract instructions vsaddu, vsadd, vssubu and vssub name vector register groups in vd, vs2 and (for the .vv form) vs1, and the RISC-V V extension requires each group to be specified by its lowest-numbered register (riscv-v-spec, Section 3.4.2). The affected Vsaddu | Vsadd | Vssubu | Vssub branch executed the arithmetic without any register-group alignment check, so reserved encodings such as vsaddu.vv v2, v1, v2 with e32/m2 (vs2=v1 misaligned) were executed. QEMU raises SIGILL for these encodings via opivv_check/opivx_check.

The fix rejects any .vv form with a misaligned vd, vs1 or vs2, and any .vx form with a misaligned vd or vs2, computing EMUL from vtype.

Validation

• cargo test --lib: the targeted saturating add/subtract alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[carlosqwqqwq]

The test-core (linux-x64) failure is a CI runner environment issue, not related to this patch.

Evidence:

1. Unrelated test: The failing test is smir::lower::runtime::jit_gate_tests::evex_fma3_register_replay::native_replay_matches_interpreter_for_rounding_sae_masks_aliases_and_llig, an x86-64 AVX-512 JIT test. This PR only touches src/isa/riscv/cpu.rs (RISC-V vector register-group alignment for the vsaddu/vsadd/vssubu/vssub family); it has no interaction with the x86 EVEX path. The test binary aborts with SIGILL (signal 4) before any assertion output.

2. Reproducible locally with full pass: On a clean checkout of master + this patch, cargo test --lib completes with 8338 passed, 0 failed (including all evex_fma3_* tests). The SIGILL cannot be reproduced locally.

3. Platform check: test-core (linux-arm64) and all test-core (macos-*) jobs pass on the same commit; only linux-x64 fails, consistently at the same AVX-512 test.

4. Runner variance: The failing runs landed on different runners (GitHub Actions 1000087925, 1000088366, 1000088537). The same AVX-512 test has passed on other PRs (e.g. fix(riscv): require aligned register groups for vssrl/vssra #285, fix(riscv): require aligned register groups for vslide1down/vfslide1down #291, fix(riscv): require aligned register groups for vsmul #292) whose diff vs. this branch differs only in src/isa/riscv/cpu.rs.

Conclusion: this is the known flaky AVX-512 JIT test on GitHub-hosted linux-x64 runners (the native replay executes AVX-512 instructions that the runner CPU does not support consistently), not a defect in this patch. The patch is unchanged apart from empty retrigger commits.

[19h]

Thanks for the report, patch, and CI follow-up. I independently reproduced the RVV issue and reimplemented the accepted alignment checks in #296. I also reran the current Linux core CI selection after rebasing onto master; it passes, including the native replay that previously raised SIGILL. The rollup includes your co-author credit and asks for your review. I’m closing this PR as superseded by #296.