fix(riscv): require aligned register groups for vaadd family

[carlosqwqqwq]

fix(riscv): require aligned register groups for vaadd family

Closes #247

Summary

The averaging add/subtract instructions vaadd, vaaddu, vasub and vasubu name vector register groups in vd, vs2 and (for the .vv form) vs1, and the RISC-V V extension requires each group to be specified by its lowest-numbered register (riscv-v-spec, Section 3.4.2). The affected Vaaddu | Vaadd | Vasubu | Vasub branch executed the arithmetic without any register-group alignment check, so reserved encodings such as vaadd.vv v2, v2, v1 with e32/m2 (vs2=v1 misaligned) were executed. QEMU raises SIGILL for these encodings via opivv_check/opivx_check.

The fix rejects any .vv form with a misaligned vd, vs1 or vs2, and any .vx form with a misaligned vd or vs2, computing EMUL from vtype.

Validation

• cargo test --lib: the targeted vaadd-family alignment tests pass, and the full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thank you for reporting #247 and proposing a fix. This is now independently consolidated in #255 for all vaadd/vaaddu/vasub/vasubu vv and vx forms, with complete LMUL group validation and legal controls across direct, SMIR/JIT, and QEMU paths. To keep review and CI focused on one rollup, I am closing this PR in favor of #255. You are credited as co-author on the rollup commit.