fix(riscv): correct Zcmp rlist=5 register count

[carlosqwqqwq]

fix(riscv): correct Zcmp rlist=5 register count

Closes #243

Summary

The RISC-V Zcmp specification maps the CM.PUSH/CM.POP rlist encoding 5 to two saved registers ({ra, s0}). The affected RAX implementation counts rlist=5 as three registers ({ra, s0, s1}) in the interpreter, in the compressed decoder, and in the SMIR lifter, so the stack adjustment is too large and s1 is spuriously saved and restored. For example, cm.push {ra, s0}, -32 (raw halfword 0xB852) produces a stack adjustment of 48 instead of the normative 32, and stores ra, s0 and s1 instead of ra and s0.

The fix corrects the register-count table in all three places so rlist=5 counts two registers and rlist=6 keeps the three-register meaning, and updates the decode and translated-path tests to the normative semantics.

Validation

• Targeted test zcmp_rlist5_saves_two_registers fails on the base checkout and passes with the fix.
• cargo test --lib: full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

[19h]

Thank you for reporting the Zcmp rlist=5 defect. I independently reproduced issue #243 against the current RISC-V Zcmp register-list and stack-adjustment tables and an LLVM decoder oracle, then reimplemented the correction across compressed decode sizing, direct execution, disassembly, and SMIR/JIT in #231.

No commits or code from this PR were taken. Your contribution is credited through the co-author trailer on the rollup commit.

I’m closing this PR as superseded by the consolidation in #231. Please review the consolidated implementation there, particularly the rlist=5/rlist=6 boundary and the RV32/RV64 stack adjustments.