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fix(riscv): canonicalize reserved mtvec MODE encodings - #230

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fix(riscv): canonicalize reserved mtvec MODE encodings#230
carlosqwqqwq wants to merge 2 commits into
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carlosqwqqwq:fix-riscv-mtvec-warl

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fix(riscv): canonicalize reserved mtvec MODE encodings

Closes #229

Summary

Writing a reserved mtvec.MODE value (2 or 3) is stored verbatim and read back verbatim. The RISC-V privileged specification defines MODE as a WARL field with legal values 0 (Direct) and 1 (Vectored); encodings >= 2 are reserved, and a WARL write of an unsupported value must be canonicalized to a legal value instead of being observable as a reserved encoding.

The fix canonicalizes the mode on write: MODE=1 stays vectored, every other encoding becomes Direct. The base address remains XLEN-masked, and existing vectored interrupt delivery is unaffected.

Validation

  • Targeted test mtvec_warl_canonicalizes_reserved_modes fails on the affected source with left: 4098, right: 4096 and passes with the fix.
  • cargo test --lib: full library test suite passes with no regressions.

No new upstream test files are added; this is a source-only change.

cpu.rs exceeded the AGENTS.md hard split triggers (2000 lines / 150 kB). Move the vector (RVV) element access and data-path execution group, including set_vtype, into cpu/vector.rs with no behavior change.

19h commented Aug 11, 2026

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Thank you for reporting and proposing this fix. I independently reimplemented and validated reserved mtvec.MODE canonicalization and WARL regression coverage in the consolidation PR #231; no commits or code from this branch were taken. The rollup carries @carlosqwqqwq as co-author on its commits and includes direct and native regression coverage. I’m closing this PR as superseded by #231—please review the consolidated implementation there.

@19h 19h closed this Aug 11, 2026
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mtvec.MODE stores reserved WARL encodings verbatim

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