fix(riscv): clear mepc bits 0-1 without C

[carlosqwqqwq]

fix(riscv): clear mepc bits 0-1 without C

Closes #225

Summary

mepc is IALIGN-WARL: with C only bit 0 is cleared, without C (IALIGN=32) bits 0-1 are cleared. The write path always cleared just bit 0, so a no-C mret could resume at a misaligned address.

Validation

• Regression writes 0x1003 to mepc under C (expect 0x1002) and under a no-C profile (expect 0x1000).
• cargo test --lib: cpu suite 70 passed, 0 failed.

Notes

Small CPU-core change; the touched group is the CSR write path (not the vector semantics split in #202).

[19h]

Thank you for reporting and proposing this fix. I independently reimplemented and validated the IALIGN-sensitive mepc WARL behavior and RV32/RV64 regression coverage in the consolidation PR #231; no commits or code from this branch were taken. The rollup carries @carlosqwqqwq as co-author on its commits and includes direct and native regression coverage. I’m closing this PR as superseded by #231—please review the consolidated implementation there.