fix(riscv): reject vector FP ops with reserved frm

[carlosqwqqwq]

fix(riscv): reject vector FP ops with reserved frm

Closes #196

Summary

The RISC-V F extension (§11.3) and RVV define frm encodings 101-111 as reserved for vector floating-point instructions: RVV takes the rounding mode from frm and does not support the dynamic mode, so any vector FP instruction executed while frm holds 101/110/111 raises an illegal-instruction exception, including operations that do not round and vl=0/vstart>=vl cases.

Validation

• Centralized Op::is_vector_fp classification next to the decoder covers every vector FP op, including vfslide1up/vfslide1down.
• CPU regression covers reserved frm 5/6/7 on vfadd, vfslide1up.vf, vfslide1down.vf, legal-frm controls, and vl=0/vstart>=vl cases.
• cargo test --lib: cpu suite 72 passed, 0 failed.

Notes

The vector semantics moved to cpu/vector.rs in #202 so this change does not grow the oversized cpu.rs.

[19h]

Blocking review finding: the new “all vector FP instructions” whitelist omits Op::Vfslide1up and Op::Vfslide1down.

Both operations are decoded in the OPFVF space (funct3=0b101), so with frm=0b101, 110, or 111 they still bypass the new guard and execute. This contradicts #196 and the RVV rule that an invalid frm is reserved for any vector floating-point instruction, including instructions unaffected by rounding and cases with vl=0 or vstart >= vl.

Please include both FP slide operations—preferably through a centralized vector-FP classification that cannot drift from the decoder—and add regression tests for reserved frm values 5, 6, and 7 plus legal controls, including vl=0/vstart >= vl. The PR currently adds no executable regression tests. Spec: https://docs.riscv.org/reference/isa/unpriv/v-st-ext

Repository policy note: this PR adds to src/isa/riscv/cpu.rs, which is currently 7,221 lines / 264,801 bytes and exceeds both hard split triggers in AGENTS.md. The touched vector semantic group should be split here or in a prerequisite shared refactor.

[carlosqwqqwq]

Thanks for the review. Reworked as suggested:

• Vfslide1up and Vfslide1down are now covered. The whitelist is replaced by a centralized Op::is_vector_fp() classification next to the decoder in src/isa/riscv/decode.rs, so the vector-FP set cannot drift from the op set.
• The reserved-frm rule now uses frm > 4 (encodings 101-111): RVV takes the rounding mode from frm and does not support the dynamic mode, so frm=7 is reserved for vector FP too.
• Added an executable regression: reserved frm 5/6/7 on vfadd.vv, vfslide1up.vf, vfslide1down.vf, legal-frm controls, and vl=0/vstart>=vl cases.
• Repository policy: the touched vector semantic group is split into src/isa/riscv/cpu/vector.rs in the prerequisite refactor refactor(riscv): split vector semantics out of cpu.rs #202.

Verified locally: cargo test --lib --no-default-features --features smir-jit cpu suite 72 passed, 0 failed.

[19h]

Thanks @carlosqwqqwq. This fix is being consolidated into rollup PR #203, where it shares centralized direct-interpreter, SMIR/JIT, and QEMU differential coverage with the related RVV corrections. Closing this PR in favor of #203; the relevant rollup commits credit you as co-author.