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Fix trace clearance checks for via drills - #505

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ZhaZhaBei:codex/via-drill-trace-clearance
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ZhaZhaBei wants to merge 1 commit into
tscircuit:mainfrom
ZhaZhaBei:codex/via-drill-trace-clearance

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Fixes #501

Summary

checkHoleTraceClearance previously considered non-plated holes but omitted via drill holes, so a trace could pass the check despite being closer than the specified trace-to-hole clearance.

  • Include via drill geometry using hole_diameter, independently of the via's outer copper diameter, while preserving the existing default behavior for other hole-geometry callers.
  • Respect the via's layer span and logical net connectivity, including through-via inner layers; avoid reporting a second drill error where an existing copper-overlap diagnostic already covers the same pair. User-facing diagnostics use readable names for named and unnamed elements.
  • Add seven regressions covering drill-edge thresholds, layer spans, connectivity across different PCB traces on the same source net, unnamed/named diagnostics, inner-layer intersection, duplicate suppression, and wire/via transitions. Update one existing fixture assertion and two SVG snapshots to reflect the newly detected physical clearances in those fixtures.

Validation

  • bun test tests/lib/check-via-drill-trace-clearance.test.ts — 7 passed, 41 assertions.
  • bun test — 760 passed, 0 failed across 248 files, 16 snapshots and 8,477 assertions.
  • ./node_modules/.bin/tsc --noEmit and bun run build — passed.
  • bun run format:check — passed; Biome reported that three pre-existing JSON files over 1 MiB were skipped by its size limit.
  • git diff --check — passed for the tracked changes.

Tests used Bun 1.4.2 on macOS arm64 with isolated HOME, temporary and cache directories and network denied during the full suite. Dependencies were installed with lifecycle scripts disabled except for the reviewed sharp native install, which ran in the isolated environment. The original issue's board and KiCad DRC results were not independently reproduced on physical hardware or in KiCad; the regression cases use synthetic circuit JSON and existing project fixtures.

AI assistance

This change and its tests were developed with AI assistance and reviewed and validated using the checks described above.

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[BUG] getHoleGeometries ignores pcb_via — checkHoleTraceClearance blind to via-track violations

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