backport RISC-V TLB/ASID enhancements with mainline SSWI support - #394

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zhuzhenxxx-collab wants to merge 16 commits into

RVCK-Project:rvck-6.6from

zhuzhenxxx-collab:rvck-6.6-tlb-asid-enhancements

Commits on Sep 20, 2026

Revert "riscv: Add ACLINT SSWI support"
ZhenXing Zhu
committed
68615b1

Commits on Sep 21, 2026

riscv: dts: thead: add TH1520 ACLINT SSWI interrupt-controller node
ZhenXing Zhu
committed
9df915e
riscv: Flush the instruction cache during SMP bringup

SiFiveHolland
authored and
ZhenXing Zhu
committed
8b6bc68
riscv: Factor out page table TLB synchronization

SiFiveHolland
authored and
ZhenXing Zhu
committed
938c165
riscv: Use IPIs for remote cache/TLB flushes by default

SiFiveHolland
authored and
ZhenXing Zhu
committed
170f040
riscv: mm: Broadcast kernel TLB flushes only when needed

SiFiveHolland
authored and
ZhenXing Zhu
committed
7bca8cc
riscv: Only send remote fences when some other CPU is online

SiFiveHolland
authored and
ZhenXing Zhu
committed
f5d2cea
riscv: mm: Combine the SMP and UP TLB flush code

SiFiveHolland
authored and
ZhenXing Zhu
committed
0d0dd08
riscv: Avoid TLB flush loops when affected by SiFive CIP-1200

SiFiveHolland
authored and
ZhenXing Zhu
committed
9f9ba18
riscv: mm: Introduce cntx2asid/cntx2version helper macros

SiFiveHolland
authored and
ZhenXing Zhu
committed
7edc8c0
riscv: mm: Use a fixed layout for the MM context ID

SiFiveHolland
authored and
ZhenXing Zhu
committed
c17978e
riscv: mm: Make asid_bits a local variable

SiFiveHolland
authored and
ZhenXing Zhu
committed
726fd1f
riscv: mm: Preserve global TLB entries when switching contexts

SiFiveHolland
authored and
ZhenXing Zhu
committed
43ca7fa
riscv: mm: Always use an ASID to flush mm contexts

SiFiveHolland
authored and
ZhenXing Zhu
committed
6925a0a
irqchip: riscv-imsic: Fixup riscv_ipi_set_virq_range() conflict

palmer-dabbelt
authored and
ZhenXing Zhu
committed
409c88f
irqchip: thead-c900-aclint-sswi: Fixup riscv_ipi_set_virq_range() conflict
ZhenXing Zhu
committed
dacebe5

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backport RISC-V TLB/ASID enhancements with mainline SSWI support - #394

backport RISC-V TLB/ASID enhancements with mainline SSWI support#394
zhuzhenxxx-collab wants to merge 16 commits into
RVCK-Project:rvck-6.6from
zhuzhenxxx-collab:rvck-6.6-tlb-asid-enhancements

Commits on Sep 20, 2026

Revert "riscv: Add ACLINT SSWI support"

Commits on Sep 21, 2026

riscv: dts: thead: add TH1520 ACLINT SSWI interrupt-controller node

riscv: Flush the instruction cache during SMP bringup

riscv: Factor out page table TLB synchronization

riscv: Use IPIs for remote cache/TLB flushes by default

riscv: mm: Broadcast kernel TLB flushes only when needed

riscv: Only send remote fences when some other CPU is online

riscv: mm: Combine the SMP and UP TLB flush code

riscv: Avoid TLB flush loops when affected by SiFive CIP-1200

riscv: mm: Introduce cntx2asid/cntx2version helper macros

riscv: mm: Use a fixed layout for the MM context ID

riscv: mm: Make asid_bits a local variable

riscv: mm: Preserve global TLB entries when switching contexts

riscv: mm: Always use an ASID to flush mm contexts

irqchip: riscv-imsic: Fixup riscv_ipi_set_virq_range() conflict

irqchip: thead-c900-aclint-sswi: Fixup riscv_ipi_set_virq_range() conflict