backport RISC-V TLB/ASID enhancements with mainline SSWI support - #394
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/35052795989 参数解析结果
测试完成 详细结果:
Kunit Test Result[03:47:00] Testing complete. Ran 482 tests: passed: 465, skipped: 17
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/35209011751 参数解析结果
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Kunit Test Result[10:14:01] Testing complete. Ran 482 tests: passed: 465, skipped: 17
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这个PR是按照同一个上游系列 riscv: ASID-related and UP-related TLB flush enhancements（Samuel Holland，v6.10）按原序的 backport，IPI 层和 TLB 层的改动在上游就是同一批代码、互相依赖。为了保持原提交的内容，在RVCK上又合入了3笔适配的提交。
已完成拆分了。riscv: Use IPIs for remote cache/TLB flushes by default 现在是与上游 dc892fb 完全一致的纯 cherry-pick（patch-id 相同），原混入其中的非上游代码4 行（SSWI 驱动 2 个调用点适配新 API 签名），已独立为末尾提交：irqchip: thead-c900-aclint-sswi: Fixup riscv_ipi_set_virq_range() conflict 该提交仿上游同类先例 46cad6c（上游在 API 变更后为 imsic 驱动补的 fixup），commit message 中已说明冲突原因和适配内容。
这组PR是上游已合入的针对性优化，和SSWI本质上没有关系，在RVCK上支持为了适配修改到了SSWI的代码。 |
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@zhuzhenxxx-collab 我看到 rvck-6.6 昨天升级了，请更新时注意 rebase 一下，谢谢 |
dist inclusion category: cleanup Link: RVCK-Project#332 -------------------------------- This reverts commit 3ea68e2 ("riscv: Add ACLINT SSWI support"). The embedded ACLINT SSWI support in sbi-ipi.c is a vendor-local implementation that never went upstream. Mainline instead provides a dedicated irqchip driver (drivers/irqchip/irq-thead-c900-aclint-sswi.c, upstream 25caea9), which has already been backported into this tree. Carrying the embedded SSWI forces downstream patches to add sswi_base- specific adaptations that diverge from mainline. Remove it so that sbi-ipi.c stays in the pure mainline form and the TLB/ASID backport series applies without conflicts. The platform keeps using SBI IPIs; the SSWI irqchip driver remains available in the tree for boards whose device trees provide the upstream "thead,c900-aclint-sswi" node. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/35489485754 参数解析结果
测试完成 详细结果:
Kunit Test Result[04:38:25] Testing complete. Ran 482 tests: passed: 465, skipped: 17
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done，麻烦再review一下 |
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我有两个问题想问一下：
@uestc-gr 请再 review 一下，谢谢 |
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lore链接已补充 |
Author
dts的修改只涉及1520 |
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riscv: dts: thead: add TH1520 ACLINT SSWI interrupt-controller node
commit message 缺少issues id 等字段
其它没有什么问题，tlb的修改建议多测试一下
Reviewed-by: Gao Rui gao.rui@zte.com.cn
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dist inclusion category: feature Link: RVCK-Project#332 -------------------------------- Add the device tree node for the T-HEAD C900 ACLINT SSWI device so that the backported mainline irqchip driver (drivers/irqchip/irq-thead-c900- aclint-sswi.c, upstream 25caea9) is probed and provides fast IPIs. The embedded SSWI support added by commit 3ea68e2 ("riscv: Add ACLINT SSWI support") has been reverted; this node uses the upstream binding "thead,c900-aclint-sswi" and the required interrupts-extended property pointing each hart at its supervisor software interrupt. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit 58661a3 ("riscv: Flush the instruction cache during SMP bringup") category: feature Link: RVCK-Project#332 -------------------------------- Instruction cache flush IPIs are sent only to CPUs in cpu_online_mask, so they will not target a CPU until it calls set_cpu_online() earlier in smp_callin(). As a result, if instruction memory is modified between the CPU coming out of reset and that point, then its instruction cache may contain stale data. Therefore, the instruction cache must be flushed after the set_cpu_online() synchronization point. Fixes: 08f051e ("RISC-V: Flush I$ when making a dirty page executable") Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-2-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit aaa56c8 ("riscv: Factor out page table TLB synchronization") category: feature Link: RVCK-Project#332 -------------------------------- The logic is the same for all page table levels. See commit 69be3fb ("riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMU"). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20240327045035.368512-3-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit dc892fb ("riscv: Use IPIs for remote cache/TLB flushes by default") category: feature Link: RVCK-Project#332 -------------------------------- An IPI backend is always required in an SMP configuration, but an SBI implementation is not. For example, SBI will be unavailable when the kernel runs in M mode. For this reason, consider IPI delivery of cache and TLB flushes to be the base case, and any other implementation (such as the SBI remote fence extension) to be an optimization. Generally, if IPIs can be delivered without firmware assistance, they are assumed to be faster than SBI calls due to the SBI context switch overhead. However, when SBI is used as the IPI backend, then the context switch cost must be paid anyway, and performing the cache/TLB flush directly in the SBI implementation is more efficient than injecting an interrupt to S-mode. This is the only existing scenario where riscv_ipi_set_virq_range() is called with use_for_rfence set to false. sbi_ipi_init() already checks riscv_ipi_have_virq_range(), so it only calls riscv_ipi_set_virq_range() when no other IPI device is available. This allows moving the static key and dropping the use_for_rfence parameter. This decouples the static key from the irqchip driver probe order. Furthermore, the static branch only makes sense when CONFIG_RISCV_SBI is enabled. Optherwise, IPIs must be used. Add a fallback definition of riscv_use_sbi_for_rfence() which handles this case and removes the need to check CONFIG_RISCV_SBI elsewhere, such as in cacheflush.c. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20240327045035.368512-4-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit 038ac18 ("riscv: mm: Broadcast kernel TLB flushes only when needed") category: feature Link: RVCK-Project#332 -------------------------------- __flush_tlb_range() avoids broadcasting TLB flushes when an mm context is only active on the local CPU. Apply this same optimization to TLB flushes of kernel memory when only one CPU is online. This check can be constant-folded when SMP is disabled. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-5-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit 9546f00 ("riscv: Only send remote fences when some other CPU is online") category: feature Link: RVCK-Project#332 -------------------------------- If no other CPU is online, a local cache or TLB flush is sufficient. These checks can be constant-folded when SMP is disabled. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20240327045035.368512-6-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit c6026d3 ("riscv: mm: Combine the SMP and UP TLB flush code") category: feature Link: RVCK-Project#332 -------------------------------- In SMP configurations, all TLB flushing narrower than flush_tlb_all() goes through __flush_tlb_range(). Do the same in UP configurations. This allows UP configurations to take advantage of recent improvements to the code in tlbflush.c, such as support for huge pages and flushing multiple-page ranges. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Yunhui Cui <cuiyunhui@bytedance.com> Link: https://lore.kernel.org/r/20240327045035.368512-7-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit d6dcdab ("riscv: Avoid TLB flush loops when affected by SiFive CIP-1200") category: feature Link: RVCK-Project#332 -------------------------------- Implementations affected by SiFive errata CIP-1200 have a bug which forces the kernel to always use the global variant of the sfence.vma instruction. When affected by this errata, do not attempt to flush a range of addresses; each iteration of the loop would actually flush the whole TLB instead. Instead, minimize the overall number of sfence.vma instructions. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Yunhui Cui <cuiyunhui@bytedance.com> Link: https://lore.kernel.org/r/20240327045035.368512-9-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit 74cd177 ("riscv: mm: Introduce cntx2asid/cntx2version helper macros") category: feature Link: RVCK-Project#332 -------------------------------- When using the ASID allocator, the MM context ID contains two values: the ASID in the lower bits, and the allocator version number in the remaining bits. Use macros to make this separation more obvious. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-10-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit f58e5dc ("riscv: mm: Use a fixed layout for the MM context ID") category: feature Link: RVCK-Project#332 -------------------------------- Currently, the size of the ASID field in the MM context ID dynamically depends on the number of hardware-supported ASID bits. This requires reading a global variable to extract either field from the context ID. Instead, allocate the maximum possible number of bits to the ASID field, so the layout of the context ID is known at compile-time. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-11-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit 8d3e761 ("riscv: mm: Make asid_bits a local variable") category: feature Link: RVCK-Project#332 -------------------------------- This variable is only used inside asids_init(). Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-12-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit 8fc21cc ("riscv: mm: Preserve global TLB entries when switching contexts") category: feature Link: RVCK-Project#332 -------------------------------- If the CPU does not support multiple ASIDs, all MM contexts use ASID 0. In this case, it is still beneficial to flush the TLB by ASID, as the single-ASID variant of the sfence.vma instruction preserves TLB entries for global (kernel) pages. This optimization is recommended by the RISC-V privileged specification: If the implementation does not provide ASIDs, or software chooses to always use ASID 0, then after every satp write, software should execute SFENCE.VMA with rs1=x0. In the common case that no global translations have been modified, rs2 should be set to a register other than x0 but which contains the value zero, so that global translations are not flushed. It is not possible to apply this optimization when using the ASID allocator, because that code must flush the TLB for all ASIDs at once when incrementing the version number. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-13-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit daef192 ("riscv: mm: Always use an ASID to flush mm contexts") category: feature Link: RVCK-Project#332 -------------------------------- Even if multiple ASIDs are not supported, using the single-ASID variant of the sfence.vma instruction preserves TLB entries for global (kernel) pages. So it is always more efficient to use the single-ASID code path. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-14-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit 46cad6c ("irqchip: riscv-imsic: Fixup riscv_ipi_set_virq_range() conflict") category: feature Link: RVCK-Project#332 -------------------------------- There was a semantic conflict between 21a8f8a ("irqchip: Add RISC-V incoming MSI controller early driver") and dc892fb ("riscv: Use IPIs for remote cache/TLB flushes by default") due to an API change. This manifests as a build failure post-merge. Reported-by: Tomasz Jeznach <tjeznach@rivosinc.com> Link: https://lore.kernel.org/all/mhng-10b71228-cf3e-42ca-9abf-5464b15093f1@palmer-ri-x1c9/ Fixes: 0bfbc91 ("Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux") Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20240522184953.28531-3-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
…flict dist inclusion category: bugfix Link: RVCK-Project#332 -------------------------------- There is a semantic conflict between the backported T-HEAD SSWI driver (upstream 25caea9) and dc892fb ("riscv: Use IPIs for remote cache/TLB flushes by default") due to the riscv_ipi_set_virq_range() API change that drops the use_for_rfence parameter. Adapt the two call sites to the new 2-parameter signature, otherwise the driver fails to build when CONFIG_THEAD_C900_ACLINT_SSWI is enabled. This mirrors upstream 46cad6c ("irqchip: riscv-imsic: Fixup riscv_ipi_set_virq_range() conflict"), which resolved the same class of conflict for the IMSIC driver. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/35553714724 参数解析结果
测试完成 详细结果:
Kunit Test Result[02:22:31] Testing complete. Ran 482 tests: passed: 465, skipped: 17
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已修改。 本地th1520 系统运行了几个小时没发现异常。 |
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LGTM
Reviewed-by: Gao Rui gao.rui@zte.com.cn
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LGTM
Reviewed-by: Chen Wang wangchen20@iscas.ac.cn
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Built and Tested boot-up on QEMU/virt + Pioneerbox. @sterling-teng 请帮忙在 th1520 上也验证一下，因为这个 PR 涉及该开发板，我手头没有这个硬件，谢谢。 |
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本 PR 将上游主线 RISC-V TLB/ASID 优化系列补丁 backport 到 rvck-6.6 基线，并同步完成 ACLINT SSWI 的主线化改造，使 TH1520 平台使用独立的 irq-thead-c900-aclint-sswi irqchip 驱动提供快速 IPI。
变更内容
TLB/ASID 优化系列 （https://lore.kernel.org/all/171569524205.4793.10651789416740480698.git-patchwork-notify@kernel.org/）
SSWI 主线化
验证结果
场景一：SSWI 开启（CONFIG_THEAD_C900_ACLINT_SSWI=y）
场景二：SSWI 关闭（# CONFIG_THEAD_C900_ACLINT_SSWI is not set，同一份 DTB）
fixes: #332