[fpga] feat: add Arty A7 Toy/Linux engineering target

.github/workflows/arty-a7-toy.yml

@@ -0,0 +1,35 @@
+name: Arty A7 Toy source and interface checks
+
+on:
+  pull_request:
+    paths:
+      - 'platforms/arty-a7-toy/**'
+      - '.github/workflows/arty-a7-toy.yml'
+  push:
+    branches: [main]
+    paths:
+      - 'platforms/arty-a7-toy/**'
+      - '.github/workflows/arty-a7-toy.yml'
+
+permissions:
+  contents: read
+
+jobs:
+  source-and-interfaces:
+    runs-on: ubuntu-24.04
+    timeout-minutes: 10
+    steps:
+      - uses: actions/checkout@11d5960a326750d5838078e36cf38b85af677262 # v4
+        with:
+          persist-credentials: false
+      - name: Verify pinned sources and recorded evidence
+        working-directory: platforms/arty-a7-toy
+        run: |
+          python3 scripts/verify_target.py
+          python3 -m compileall -q scripts tests host software
+          bash -n scripts/elaborate.sh scripts/build_test_programs.sh software/build.sh
+      - name: Install interface simulator
+        run: sudo apt-get update && sudo apt-get install -y iverilog
+      - name: AXI, UART/SCU and DDR loader interface tests
+        working-directory: platforms/arty-a7-toy
+        run: timeout --signal=TERM --kill-after=15s 180s python3 scripts/check_board.py

README.md

@@ -8,11 +8,16 @@ This repo is where we put [Buckyball](https://github.com/DangoSys/buckyball) ont
 |---|---|---|
 | Kintex-7 | `xc7k160tffg676-2` | [Existing P2E flow](platforms/xc7k160t/README.md) |
 | Digilent Arty A7-100T | `xc7a100tcsg324-1` | [Standalone CPU/BRAM/UART platform](platforms/arty-a7/README.md) |
+| Digilent Arty A7-100T, Toy/Linux | `xc7a100tcsg324-1` | [CPU/Sv39/FPU/Gemmini 8×8 with DDR](platforms/arty-a7-toy/README.md) |
 
-The Arty A7 platform has its own pinned Chisel build, serial loader, firmware,
+The Arty A7 platforms have their own pinned Chisel build, serial loader, firmware,
 constraints and verification record. Follow its guide directly; the setup and
 demo below describe the existing Kintex-7 flow.
 
+The Toy/Linux target passes complete board implementation and Linux RTL checks.
+Its current Rev E DDR engineering target still requires physical DDR calibration
+and Linux boot acceptance; see its guide before programming.
+
 ## Kintex-7 setup
 
 First, build the repository with these steps:

platforms/arty-a7-toy/.gitattributes

@@ -0,0 +1,7 @@
+# Preserve original source, vendor and measured-evidence bytes for hash checks.
+* -text
+* whitespace=trailing-space,space-before-tab,cr-at-eol
+# Do not rewrite whitespace in upstream snapshots or raw tool output.
+board/vendor/** -whitespace
+tests/reference/** -whitespace
+evidence/** -whitespace

platforms/arty-a7-toy/.gitignore

@@ -0,0 +1,12 @@
+/upstream/
+/thirdparty/
+/build/
+/target/
+/project/target/
+/project/project/
+__pycache__/
+.Xil/
+*.log
+!evidence/**/*.log
+*.jou
+toy-console.log

platforms/arty-a7-toy/.jvmopts

@@ -0,0 +1,4 @@
+-Xmx12G
+-Xss8M
+-XX:ActiveProcessorCount=8
+-Dsbt.supershell=false

platforms/arty-a7-toy/README.md

@@ -0,0 +1,102 @@
+# Toy/Linux on Arty A7-100T
+
+A Chisel-generated Toy platform for `xc7a100tcsg324-1`, with CPU, Sv39, full
+FP16/32/64 support and Gemmini 8×8. Complete board implementation, timing, CDC
+checks and Linux RTL tests pass. The physical board revision is unconfirmed:
+this is a **Rev E engineering bring-up target**, awaiting hardware DDR and Linux
+acceptance. See [measured results](VALIDATION.md) before programming.
+
+## Architecture and scope
+
+- RV64IMAFDC with Zfh/Zba/Zbb/Zbs, M/S/U, PMP, Sv39, interrupts and 8 KiB I/D
+  caches. FP16/32/64 share the FMA; the register file uses validated LUTRAM.
+- Gemmini 8×8 OS/WS, 64 DSP PE MACs, 64 KiB accelerator SRAM and 23 opcodes.
+  Group-query ownership, simultaneous SubROB enqueue/retirement, WS bias and
+  rounding fixes are included as Chisel overrides.
+- 256 MiB DDR3L at `0x80000000`, official Digilent Rev E MIG, real Xilinx AXI
+  Clock Converter and a byte-strobe preserving fullwidth DDR adapter.
+- 100 MHz oscillator, 25 MHz CPU, 83.33 MHz MIG UI, 500 kHz CLINT; UART 1 Mbps
+  8N1. SCU exit/TX/RX/status: `0x60000000`, `0x60020000/04/05`.
+
+This is the previously evaluated FPGA profile, not the default full-size Toy:
+other Balls, L2, BTB, debug, extra performance counters and the separate TL
+scratchpad are absent; broadcast coherence and basic counters remain. Accelerator
+SRAM is distinct from that removed TL scratchpad. No software emulation is
+silently substituted. The current PR adds no further core cuts.
+
+Pinned upstream files are restored into ignored `upstream/`; dependencies into
+ignored `thirdparty/`. `patches/` contains the hardware overrides, `src/` the
+top/configuration, `rtl/` memory/RF adapters, `board/` physical integration,
+`software/` pinned Linux/OpenSBI preparation, and `tests/` independent oracles.
+
+## Build
+
+Run from this directory on Linux with Python 3.12+, Git, curl, JDK 17, sbt,
+firtool 1.62.1, RV64 bare-metal and Linux GCC/binutils, Verilator, Icarus Verilog,
+and Vivado with Artix-7 support. Kernel builds also need CMake, Make, flex,
+bison and the standard kernel development libraries. The tested tool versions
+and byte hashes are recorded in `evidence/2026-10-11/`.
+
+```bash
+cd platforms/arty-a7-toy
+# Optional --repository reuses pinned Git objects without changing that checkout.
+bash scripts/elaborate.sh --repository ../../thirdparty/buckyball
+bash scripts/build_test_programs.sh
+timeout --signal=TERM --kill-after=15s 3600s python3 scripts/run_board_regression.py
+python3 scripts/start_board_build.py
+```
+
+Omit `--repository` to fetch a private pinned Git cache. Chisel 6.7.0 and Scala
+2.13.16 are set by `build.sbt`; sbt is pinned in `project/build.properties`.
+Set `CHISEL_FIRTOOL_PATH` to the directory containing firtool when required.
+`scripts/verify_target.py --core` rejects a regenerated core or SRAM/RF binding
+whose bytes differ from the validated version.
+
+The board launcher returns immediately with a fresh output directory. Inspect
+its `RUN.json`, `phase.txt` and `vivado.log` until status is `COMPLETED`, exit code
+0 and `bitstream_generated` true. The entire Vivado process group has a
+3,600-second timeout plus 15-second termination grace. Timing, CDC, bus-skew,
+routing and DRC failures prevent bitstream generation. `VIVADO` may point to an
+installed compatibility wrapper; otherwise `vivado` is resolved on PATH.
+
+```bash
+bash software/build.sh
+python3 scripts/build_board_firmware.py
+timeout --signal=TERM --kill-after=15s 3600s python3 scripts/check_board_linux.py
+timeout --signal=TERM --kill-after=15s 1800s python3 scripts/check_board_uart_boot.py
+python3 scripts/check_board_cdc.py board-YYYYMMDD-HHMMSS --output-name board-cdc-new
+```
+
+Use the actual board run name for CDC testing and a fresh simulation output
+name. OpenSBI rebuild defaults to `riscv64-linux-gnu-`; `--cross-compile` selects
+another compatible GNU prefix. `--software-base` can reuse another isolated root
+containing `build/software` produced by the same pinned software flow.
+
+Generated RTL, firmware, dependencies, checkpoints and bitstreams are build
+products and are not committed. A successful fresh board run produces
+`build/board-<timestamp>/toy_a7.bit`; the Linux payload is
+`build/board-software/fw_payload.bin`.
+
+## First hardware boot
+
+1. Confirm the physical DDR/revision matches the official Rev E parameters;
+   connect PROG/UART USB and select the single XC7A100T in Hardware Manager.
+2. Program the selected `.bit` into volatile FPGA SRAM. On Windows:
+   `./program.ps1 -Bitstream <absolute-bitstream-path> -VivadoBin <Vivado-bin>`.
+   The script does not write flash and is not run automatically.
+3. Press BTN0, wait for LED0 (DDR calibrated), and close other serial clients.
+4. Install `pyserial`, then load and byte-verify the image before releasing CPU:
+
+```bash
+python host/load.py --port COM5 --check-linux build/board-software/fw_payload.bin
+```
+
+Use the actual serial port. Expect OpenSBI, Linux, BusyBox and five PASS markers
+for COW, page protection, FP64 process context, the timer and the total Linux
+system check. A 17 MiB transfer with full readback takes several minutes at
+1 Mbps. After the script closes the port, an interactive console is available
+with `python -m serial.tools.miniterm COM5 1000000 --eol LF`.
+
+LED1 indicates loader error or nonzero exit, LED2 CPU released, LED3 heartbeat.
+LEDs alone do not establish software success. Preserve the console transcript
+and DDR calibration result; operator acceptance additionally needs Gemmini tests.

platforms/arty-a7-toy/SOFTWARE_BASELINE.json

@@ -0,0 +1,6 @@
+{
+  "bbkernel": "b80336ce647f6604713f1570e1e1355f705a4355",
+  "linux": "ffc253263a1375a65fa6c9f62a893e9767fbebfa",
+  "opensbi": "c0f87f10d1bfb9e72a84ddfafb5604ee1bfe9d04",
+  "busybox": "1a64f6a20aaf6ea4dbba68bbfa8cc1ab7e5c57c4"
+}