[fpga] feat: add Arty A7 Toy/Linux engineering target

[Cody-ic]

Add a separate Arty A7-100T Toy/Linux engineering target with a Chisel-generated CPU, Sv39, full FP16/32/64 support and Gemmini 8×8. The board integrates DDR, clock/reset generation, AXI clock conversion, SCU console and a CRC UART loader that verifies the image before releasing the CPU.

Changes

• Pinned Chisel/dependency builds, explicit source digests, FPGA SRAM/RF bindings and DSP PE/shared-FMA overrides.
• Gemmini group-query, SubROB, WS bias/loop and rounding corrections, with preserved reference oracles.
• Official Digilent Rev E MIG inputs, board constraints, portable one-hour implementation launcher, loading/programming instructions and pinned Linux/OpenSBI preparation.
• Original implementation reports and RTL test evidence; lightweight CI checks source hashes and AXI/SCU/loader interfaces.

Validation

• Complete Vivado 2024.1 implementation: 54,413 LUT, 35,600 FF, 29 BRAM tiles, 117 DSP, including all 64 PE DSPs.
• 25 MHz; WNS +1.276 ns, WHS +0.013 ns; all 95,231 nets routed, zero route errors and CDC Critical findings. Ten bus-skew constraints pass; no DRC Error/Critical Warning.
• CPU/Sv39/FPU/AMO/cache/interrupt, original Gemmini 13/13, 40 OS/WS loops and unaligned/cross-page DMA pass through board RTL.
• UART RTL loads and reads back 110,592 bytes before RUN; the original CPU oracle passes without preloaded DDR or forced release.
• OpenSBI/Linux 6.6/BusyBox RTL boot passes COW, page protection, FP64 process-context and timer checks.
• Relocated repository package recompiles Chisel and OpenSBI to the same validated core/RAM/payload bytes; interface and syntax checks pass. Gitleaks 8.30.1 finds no secrets; a source-checksum false positive was resolved by explicitly labeling digests, without scanner exclusions.

Hardware acceptance and merge scope

This PR lands an engineering bring-up target; merging it does not mark hardware acceptance complete. The physical PCB revision is unconfirmed. Rev E DDR calibration, physical Linux boot and operator execution remain to be tested. Simulations replace the DDR PHY with a stalled AXI memory model; they do not establish hardware success.

Occupied Slice sites are 15,663/15,850 (98.82%), leaving only 187; LUT headroom is not placement headroom. Remaining vendor/methodology warnings and Gemmini coverage limits are documented in VALIDATION.md. This profile retains 23 Gemmini opcodes, with the previously evaluated cache/coherence/peripheral reductions; it is not the default full-size Toy configuration.

Generated RTL, dependencies, firmware, checkpoints and bitstreams are build products, not committed binaries. The validated engineering bitstream and payload hashes are recorded for first bring-up.