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x86_64 asm: load 32-bit parameters as 32-bit and ArrowLake/LunarLake change #11986

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x86_64 asm: load 32-bit parameters as 32-bit and ArrowLake/LunarLake change #11986

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2 changes: 2 additions & 0 deletions .wolfssl_known_macro_extras
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Original file line number Diff line number Diff line change
Expand Up @@ -835,6 +835,7 @@ WC_ASYNC_THREAD_BIND
WC_BENCH_AES_IV_SWEEP
WC_BLINDING_NO_RNG_ACKNOWLEDGE_WEAKNESS
WC_CACHE_RESISTANT_BASE64_TABLE
WC_CPUID_NO_TUNING
WC_DISABLE_RADIX_ZERO_PAD
WC_DRBG_BANKREF
WC_FIPS_ED25519CTX_NOT_APPROVED
Expand Down Expand Up @@ -1506,6 +1507,7 @@ __ghc__
__ghs__
__has_attribute
__has_include
__has_warning
__hpux__
__i386
__i386__
Expand Down
442 changes: 440 additions & 2 deletions tests/unit-mcdc/test_aes_whitebox.c
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6 changes: 5 additions & 1 deletion tests/unit-mcdc/test_sha3_whitebox.c
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Expand Up @@ -108,13 +108,17 @@ static void wb_sha3_dispatch(void)
wb_init_with(CPUID_BMI1, NULL); /* [T,F] */
wb_init_with(0, NULL); /* [F,-] -> C block */

/* SHA3_USE_AVX2(f) = IS_INTEL_AVX2(f) && IS_CPU_INTEL(f).
/* SHA3_USE_AVX2(f) = IS_INTEL_AVX2(f) && IS_CPU_INTEL(f) &&
* !IS_CPU_SLOW_AVX2_SHA3(f).
* The [T,T] row cannot come from real cpuid on a non-Intel host, so
* neither operand's pair completes without forcing the vendor bit:
* AVX2-capable AMD reports [T,F], the same row as the AVX2-only call
* above. Supply [T,T]; it pairs with CPUID_AVX2 ([T,F]) for operand 1
* and with the BMI rows ([F,-]) for operand 0. */
wb_init_with(CPUID_AVX2 | CPUID_INTEL, NULL);
/* Third operand, !IS_CPU_SLOW_AVX2_SHA3(f): [T,T,T] pairs with the row
* above for its independence (Arrow Lake: AVX2 Keccak skipped). */
wb_init_with(CPUID_AVX2 | CPUID_INTEL | CPUID_SLOW_AVX2_SHA3, NULL);

/* 874: (sha3_block_n != NULL) && (blocks > 0), in Sha3Update. MC/DC needs
* cond0's independence pair -- both the NULL and non-NULL multi-block
Expand Down
13 changes: 10 additions & 3 deletions tests/unit-mcdc/test_wc_mldsa_whitebox.c
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Expand Up @@ -1076,9 +1076,12 @@ static void wb_dispatch_rows(void)
/* USE_INTEL_AVX512(f) is itself IS_INTEL_AVX512(f) && IS_INTEL_AVX512_BW(f)
* (cpuid.h), so each AVX512 dispatch is a three-condition decision and the
* F and BW bits need to be cleared separately. SHA3_USE_AVX2(f) is
* IS_INTEL_AVX2(f) && IS_CPU_INTEL(f): its vendor operand is false on any
* AMD host, so CPUID_INTEL is forced on for the rows that need its true
* side -- the arm behind it is plain AVX2, which runs anywhere AVX2 does. */
* IS_INTEL_AVX2(f) && IS_CPU_INTEL(f) && !IS_CPU_SLOW_AVX2_SHA3(f): its
* vendor operand is false on any AMD host, so CPUID_INTEL is forced on for
* the rows that need its true side -- the arm behind it is plain AVX2,
* which runs anywhere AVX2 does. The host's tuning bits are cleared on
* every row so the rows mean the same on Arrow Lake, and one row sets
* CPUID_SLOW_AVX2_SHA3 for that operand's true side. */
static const struct {
cpuid_flags_t set;
cpuid_flags_t clear;
Expand Down Expand Up @@ -1106,6 +1109,9 @@ static void wb_dispatch_rows(void)
CPUID_AVX512_VBMI | CPUID_BMI2 |
CPUID_AVX2, 0 }, /* portable C */
{ 0, CPUID_INTEL, 0 }, /* non-Intel vendor */
{ CPUID_INTEL | CPUID_SLOW_AVX2_SHA3,
CPUID_AVX512 | CPUID_AVX512_BW |
CPUID_AVX512_VBMI, 0 }, /* AVX2, slow Keccak */
};

if (wc_InitRng(&rng) != 0) {
Expand All @@ -1116,6 +1122,7 @@ static void wb_dispatch_rows(void)
for (i = 0; i < sizeof(rows) / sizeof(rows[0]); i++) {
cpuid_flags = WC_CPUID_INITIALIZER;
(void)cpuid_get_flags_ex(&cpuid_flags);
cpuid_flags &= (cpuid_flags_t)~(CPUID_SLOW_VAES | CPUID_SLOW_AVX2_SHA3);
cpuid_flags |= rows[i].set;
cpuid_flags &= (cpuid_flags_t)~rows[i].clear;
wb_intr_ret = rows[i].intr;
Expand Down
2 changes: 2 additions & 0 deletions wolfcrypt/benchmark/benchmark.c
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Expand Up @@ -5168,6 +5168,8 @@ static void print_cpu_features(void)
if (IS_INTEL_SHA(cpuid_flags)) printf(" sha");
if (IS_INTEL_VAES(cpuid_flags)) printf(" vaes");
if (IS_INTEL_AVX512(cpuid_flags)) printf(" avx512");
if (IS_CPU_SLOW_VAES(cpuid_flags)) printf(" (slow-vaes)");
if (IS_CPU_SLOW_AVX2_SHA3(cpuid_flags)) printf(" (slow-avx2-sha3)");
#endif
#ifdef __aarch64__
printf("Aarch64 -");
Expand Down
123 changes: 65 additions & 58 deletions wolfcrypt/src/aes.c
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10 changes: 5 additions & 5 deletions wolfcrypt/src/aes_gcm_asm.asm
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Expand Up @@ -3822,7 +3822,7 @@ AES_GCM_init_aesni PROC
push r13
push r14
mov rdi, rcx
mov rsi, rdx
mov esi, edx
mov r10, r8
mov r11d, r9d
mov rax, QWORD PTR [rsp+80]
Expand Down Expand Up @@ -10519,7 +10519,7 @@ AES_GCM_init_avx1 PROC
push r12
push r13
mov rdi, rcx
mov rsi, rdx
mov esi, edx
mov r10, r8
mov r11d, r9d
mov rax, QWORD PTR [rsp+72]
Expand Down Expand Up @@ -16564,7 +16564,7 @@ AES_GCM_init_avx2 PROC
push rsi
push r12
mov rdi, rcx
mov rsi, rdx
mov esi, edx
mov r10, r8
mov r11d, r9d
mov rax, QWORD PTR [rsp+72]
Expand Down Expand Up @@ -23105,7 +23105,7 @@ AES_GCM_init_vaes PROC
push r12
push r13
mov rdi, rcx
mov rsi, rdx
mov esi, edx
mov r10, r8
mov r11d, r9d
mov rax, QWORD PTR [rsp+72]
Expand Down Expand Up @@ -32825,7 +32825,7 @@ AES_GCM_init_avx512 PROC
push r12
push r13
mov rdi, rcx
mov rsi, rdx
mov esi, edx
mov r10, r8
mov r11d, r9d
mov rax, QWORD PTR [rsp+72]
Expand Down
32 changes: 16 additions & 16 deletions wolfcrypt/src/aes_xts_asm.S
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Expand Up @@ -133,7 +133,7 @@ _AES_XTS_encrypt_aesni:
#endif /* __APPLE__ */
pushq %r12
pushq %r13
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r12
movl 24(%rsp), %r10d
subq $0x48, %rsp
Expand Down Expand Up @@ -456,7 +456,7 @@ WC_ASM_ATT_HIDDEN(_AES_XTS_encrypt_update_aesni)
_AES_XTS_encrypt_update_aesni:
#endif /* __APPLE__ */
pushq %r12
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r10
subq $0x40, %rsp
movdqu L_aes_xts_gc_xts(%rip), %xmm12
Expand Down Expand Up @@ -744,7 +744,7 @@ _AES_XTS_decrypt_aesni:
#endif /* __APPLE__ */
pushq %r12
pushq %r13
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r12
movl 24(%rsp), %r10d
subq $24, %rsp
Expand Down Expand Up @@ -1121,7 +1121,7 @@ WC_ASM_ATT_HIDDEN(_AES_XTS_decrypt_update_aesni)
_AES_XTS_decrypt_update_aesni:
#endif /* __APPLE__ */
pushq %r12
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r10
subq $16, %rsp
movdqu L_aes_xts_gc_xts(%rip), %xmm12
Expand Down Expand Up @@ -1531,7 +1531,7 @@ _AES_XTS_encrypt_avx1:
#endif /* __APPLE__ */
pushq %r12
pushq %r13
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r12
movl 24(%rsp), %r10d
subq $0x48, %rsp
Expand Down Expand Up @@ -1845,7 +1845,7 @@ WC_ASM_ATT_HIDDEN(_AES_XTS_encrypt_update_avx1)
_AES_XTS_encrypt_update_avx1:
#endif /* __APPLE__ */
pushq %r12
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r10
subq $0x40, %rsp
vmovdqu L_avx1_aes_xts_gc_xts(%rip), %xmm12
Expand Down Expand Up @@ -2124,7 +2124,7 @@ _AES_XTS_decrypt_avx1:
#endif /* __APPLE__ */
pushq %r12
pushq %r13
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r12
movl 24(%rsp), %r10d
subq $24, %rsp
Expand Down Expand Up @@ -2490,7 +2490,7 @@ WC_ASM_ATT_HIDDEN(_AES_XTS_decrypt_update_avx1)
_AES_XTS_decrypt_update_avx1:
#endif /* __APPLE__ */
pushq %r12
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r10
subq $16, %rsp
vmovdqu L_avx1_aes_xts_gc_xts(%rip), %xmm12
Expand Down Expand Up @@ -2928,7 +2928,7 @@ _AES_XTS_encrypt_vaes:
#endif /* __APPLE__ */
pushq %r12
pushq %r13
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r12
movl 24(%rsp), %r10d
subq $0x48, %rsp
Expand Down Expand Up @@ -3429,7 +3429,7 @@ WC_ASM_ATT_HIDDEN(_AES_XTS_encrypt_update_vaes)
_AES_XTS_encrypt_update_vaes:
#endif /* __APPLE__ */
pushq %r12
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r10
subq $0x40, %rsp
vmovdqu L_vaes_aes_xts_gc_xts(%rip), %xmm12
Expand Down Expand Up @@ -3895,7 +3895,7 @@ _AES_XTS_decrypt_vaes:
#endif /* __APPLE__ */
pushq %r12
pushq %r13
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r12
movl 24(%rsp), %r10d
subq $0x48, %rsp
Expand Down Expand Up @@ -4470,7 +4470,7 @@ WC_ASM_ATT_HIDDEN(_AES_XTS_decrypt_update_vaes)
_AES_XTS_decrypt_update_vaes:
#endif /* __APPLE__ */
pushq %r12
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r10
subq $0x40, %rsp
vmovdqu L_vaes_aes_xts_gc_xts(%rip), %xmm12
Expand Down Expand Up @@ -5121,7 +5121,7 @@ _AES_XTS_encrypt_avx512:
#endif /* __APPLE__ */
pushq %r12
pushq %r13
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r12
movl 24(%rsp), %r10d
subq $0x48, %rsp
Expand Down Expand Up @@ -5629,7 +5629,7 @@ WC_ASM_ATT_HIDDEN(_AES_XTS_encrypt_update_avx512)
_AES_XTS_encrypt_update_avx512:
#endif /* __APPLE__ */
pushq %r12
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r10
subq $0x40, %rsp
vmovdqu L_avx512_aes_xts_gc_xts(%rip), %xmm12
Expand Down Expand Up @@ -6102,7 +6102,7 @@ _AES_XTS_decrypt_avx512:
#endif /* __APPLE__ */
pushq %r12
pushq %r13
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r12
movl 24(%rsp), %r10d
subq $0x48, %rsp
Expand Down Expand Up @@ -6694,7 +6694,7 @@ WC_ASM_ATT_HIDDEN(_AES_XTS_decrypt_update_avx512)
_AES_XTS_decrypt_update_avx512:
#endif /* __APPLE__ */
pushq %r12
movq %rdx, %rax
movl %edx, %eax
movq %rcx, %r10
subq $0x40, %rsp
vmovdqu L_avx512_aes_xts_gc_xts(%rip), %xmm12
Expand Down
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