[SparkiDev]

Description

MIPS Release 6 removed the HI/LO registers and the multu/dmultu, mflo and mfhi instructions. The SP int MIPS and MIPS64 assembly used them and listed $hi/$lo as clobbers, so builds for r6 CPUs failed with "the register '$hi' cannot be clobbered".

Add SP_ASM_MIPS_MUL to put the low and high words of a multiplication into registers. Use mulu/muhu (dmulu/dmuhu for 64-bit) when __mips_isa_rev >= 6 and the existing multu/mflo/mfhi sequence otherwise. Only clobber HI/LO before r6. Mark the high word output as early clobber in the macros that write the result directly, as r6 writes it before the inputs are fully consumed.

Code generated for pre-r6 targets is unchanged.

Fixes #11953

Testing

The patched source was cross-built with ./configure --host=<mips triplet> --enable-all --disable-shared using zig 0.14.1 cc (clang-based, musl libc) as the compiler. wolfcrypt/test/testwolfcrypt was then run under qemu-user.

Target	configure define	qemu CPU	Multiply instructions in sp_int.o	testwolfcrypt
mips64r6el, n64	WOLFSSL_SP_MIPS64	I6400	dmulu/dmuhu	Pass
mips64r6el, n32	WOLFSSL_SP_MIPS64	I6400	dmulu/dmuhu	Pass
mips32r6el	WOLFSSL_SP_MIPS	mips32r6-generic	mulu/muhu	Pass
mips32r2el (regression)	WOLFSSL_SP_MIPS	24Kf	multu/mflo/mfhi	Pass

[Copilot]

🔵 Needs a closer look

The cryptographic assembly changes across MIPS32 and MIPS64 n32/n64 need GCC cross-build and runtime validation, since Clang-only results do not confirm the compiler-specific register constraints implicated in the original GCC failure.

No open issues 🎉

What changed in this PR

Adds MIPS Release 6 support to wolfCrypt’s SP integer assembly, addressing the build failure caused by removed HI/LO registers and instructions in #11953.

Changes:

• Uses mulu/muhu and dmulu/dmuhu on Release 6, retaining legacy multiply sequences on older targets.
• Makes HI/LO clobbers conditional on the ISA revision.
• Adds early-clobber constraints to high-word outputs to prevent input-register overlap.

File	Description
wolfcrypt/​src/​sp_int.c	Updates MIPS32 and MIPS64 multiply and square macros for Release 6 compatibility.

_{Review effort: Balanced}

[github-actions]

MemBrowse Memory Report · Explore what changed →

zephyr-frdm_rw612

• FLASH: log_const_area -8 B, rodata -8 B, text +1,560 B (+0.5%, 284,008 B / 67,108,864 B, total: 0% used)

No memory changes detected for:

• gcc-arm-cortex-m0plus
• gcc-arm-cortex-m3
• gcc-arm-cortex-m4
• gcc-arm-cortex-m4-baremetal
• gcc-arm-cortex-m4-crypto-only
• gcc-arm-cortex-m4-dtls13
• gcc-arm-cortex-m4-min-ecc
• gcc-arm-cortex-m4-openssl-compat
• gcc-arm-cortex-m4-pkcs7
• gcc-arm-cortex-m4-pq
• gcc-arm-cortex-m4-rsa-only
• gcc-arm-cortex-m4-sp-math
• gcc-arm-cortex-m4-tls12
• gcc-arm-cortex-m4-tls13
• gcc-arm-cortex-m7
• gcc-arm-cortex-m7-pq
• gcc-arm-cortex-m7-tls13
• stm32-sim-stm32h753

---

_{Catch memory regressions in CI with MemBrowse. Free for open source.}

[SparkiDev]

Jenkins: retest this please

[SparkiDev]

Jenkins: retest this please

[SparkiDev]

Jenkins: retest this please