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add simple verilog models for clocking components - #199

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cedard234 wants to merge 1 commit into
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add simple verilog models for clocking components#199
cedard234 wants to merge 1 commit into
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dw/clocking_models

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@cedard234

@cedard234 cedard234 commented Sep 10, 2026

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WiP on PLL model now

@cedard234 cedard234 self-assigned this Sep 10, 2026

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@rahulk29 rahulk29 Awaiting requested review from rahulk29
@rohanku rohanku Awaiting requested review from rohanku
@roshanparekh roshanparekh Awaiting requested review from roshanparekh

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