[CUDA] SM120 block-scaled register-A GEMM: unroll K atoms and load scales once per atom - #3286
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…ales once per atom The SM120 block-scaled lowering with A in a register fragment (is_gemm_rs) looped over the K atoms of a call with a runtime index. Once the A fragment spans more than one 64-wide K atom, that index forces the whole fragment into local memory (spills on the MMA path). Unroll the K-atom loop in TIR (T.unroll(explicit=True)) so every fragment access has a compile-time index. TensorCoreIntrinEmitterSM120.mma() read both scale words from shared memory for every MMA. When both scale buffers are in shared memory, load one compact selector package per lane and K atom instead (the scheme the full-tile K-major path already uses) and let each MMA pick the owning lane through its scale thread-id operand: ceil(warp_rows / 2) SFA words and ceil(n8_blocks / 4) SFB words per lane instead of three shared loads per MMA pair. Both row-major and chunk K-major scale layouts are handled; fragment scales keep the existing path. The MMA sequence and the scale values each MMA consumes are unchanged, so results are bit-identical. Tests: register-A multi-atom cases (K=192/256, FullRow/Square/FullCol, transposed A) and a shared-A rowmajor K=192 case in the fragments/odd-warps correctness test, plus a codegen test that the K-atom loop is gone and the MMAs read scale packages. Adds maint/gemm/gemm_sm120/benchmark_sm120_nvfp4_fragment_a_gemm.py for the register-A path.
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Included review availability: This review used your included allowance. Your plan provides up to 8 included reviews per hour; 6 remain after this review. 📝 WalkthroughWalkthroughThis change updates SM120 block-scaled MMA code generation, adds fragment-A test coverage, and introduces a standalone NVFP4 fragment-A GEMM benchmark with optional result verification. ChangesSM120 NVFP4 block-scaled GEMM
Priority: ➖ Normal Estimated code review effort: 3 (Moderate) | ~25 minutes Change: Bug fix Sequence Diagram(s)sequenceDiagram
participant CLI
participant Benchmark
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CLI->>Benchmark: pass dimensions and launch options
Benchmark->>TileLangKernel: build and invoke GEMM
Benchmark->>CUDA: create seeded inputs and scales
Benchmark->>Benchmark: optionally verify output and measure latency
Merge Risk: ⚪ Minimal · up to No actionable current-head regression is established. The remaining scale-scope concern predates this change, and the benchmark safely handles partial M/N tiles, so mergeability risk is minimal. Security Architecture ReviewSecurity architecture risk: 🔵 Low · up to The change stays within GPU kernel generation and does not add a new external entrypoint or privilege. Its main risk is incorrect scale selection in generated kernels; the source mapping and added tests provide reassurance, but execution across all supported configurations has not been established here. Retained concerns Security review detailsSecurity Blast Radius
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In @maint/gemm/gemm_sm120/benchmark_sm120_nvfp4_fragment_a_gemm.py:
- Around line 96-148: Add argument validation in main after parsing arguments
and before calling fragment_a_blockscaled_gemm: require --block-k and --k to be
divisible by 64, and require --k to be divisible by --block-k. Use parser.error
for invalid configurations so they are rejected before kernel compilation.
In @tilelang/cuda/intrinsics/macro/mma_sm120_macro_generator.py:
- Around line 619-629: Add a scope check before the compact dispatch in the
non-fragment branch of the SM120 MMA generator: require both SFA_data and
SFB_data to be shared or shared.dyn, and raise ValueError otherwise. Keep the
existing _mma_with_compact_scale_packages call for valid scopes.
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maint/gemm/gemm_sm120/benchmark_sm120_nvfp4_fragment_a_gemm.pytesting/python/language/test_tilelang_language_nvf4_mma_block_scale.pytilelang/cuda/intrinsics/macro/mma_sm120_macro_generator.pytilelang/cuda/op/gemm/gemm_mma_sm120.py
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…date benchmark K arguments Address review: the compact selector-package path reads scales from shared memory, so dispatch to it only when both SFA and SFB are shared buffers and keep the existing per-MMA path for every other scope. The fragment-A benchmark now rejects --k / --block-k values that are not multiples of the 64-wide K atom, or a --k that is not a multiple of --block-k.
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Hi all, a bit of context on where these PRs come from and where I'd like to take them. I'm Hamza from Horizon Tech. I've been fully behind TileLang since the moment I first read about it, and I'd like to become a long-term contributor here, not just someone who opens a few PRs. I work with RTX PRO 6000 Blackwell GPUs (SM120, 96 GB), serving Qwen3.8-27B in vLLM. When I started, SM120 was poorly served for NVFP4:
Since then, with kernels written in TileLang, the same card serves 143 tok/s for 1 user (+28% over Marlin) and ~835 tok/s for 8 users (+18%). The FP4 prefill GEMM (two-pass residual NVFP4 on the native tensor cores) runs 1.5–1.9× faster than Marlin at 512–8,192 tokens, and quality holds in paired GSM8K / MMLU-Pro evals and log-prob checks. Part of the end-to-end gain comes from a retrained speculative-decoding draft head, but the core is the TileLang kernels, and that's the part I want to bring upstream:
What you can expect from me going forward:
My goal is simple: get as much performance out of this hardware as possible, and land it upstream so everyone benefits. I'm happy to adapt to however you prefer contributions structured. Since these are my first PRs here, CI needs a maintainer's approval to run whenever someone has a moment. |
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Summary
Follow-up to #3257, which added
T.gemm_blockscaled/T.mma_gemm_blockscaledwith A taken from a register fragment onSM120 (
is_gemm_rs). Two lowering issues show up as soon as the A fragment spans more than one 64-wide K atom:GemmMMASm120BlockScaled.loweriterated the K atoms of a call withT.serial, so every fragment access used a runtime index. nvcc then keeps the fragment in local memory (spills on theMMA path) whenever it does not unroll that loop itself, which happens in pipelined and warp-specialized kernels.
The loop is now
T.unroll(..., explicit=True): every access has a compile-time index.TensorCoreIntrinEmitterSM120.mma()passed shared-memorypointers for SFA and SFB to each
mma.sync ... block_scale(three shared loads per MMA pair). When both scale buffersare in shared memory it now loads one compact selector package per lane and K atom, the scheme the full-tile K-major
path already uses: lanes
tandt ^ 1of a quad hold the SFA rows of MMA atom rows2g/2g + 1, quad laneqholds the SFB columns of n8 block
4g + q, and each MMA picks the owning lane with its scale thread-id operand. Thatis
ceil(warp_rows / 2)SFA words andceil(n8_blocks / 4)SFB words per lane per atom. Row-major and chunk-K-majorscale layouts are both handled; fragment scales keep the existing path.
The MMA sequence and the scale value each MMA consumes are unchanged, so results are bit-identical to
main. Thefull-tile K-major path (
sf_layout="blockscaled_chunk_kmajor", used byexamples/gemm_sm120and the maint benchmark)is not touched.
Changes
tilelang/cuda/op/gemm/gemm_mma_sm120.py: the register-A branch unrolls the K-atom loop in TIR.tilelang/cuda/intrinsics/macro/mma_sm120_macro_generator.py:mma()dispatches to a new_mma_with_compact_scale_packages()when SFA and SFB are both shared buffers.testing/python/language/test_tilelang_language_nvf4_mma_block_scale.py:test_nvf4_mma_block_scale_fragments_and_odd_warps: register A with K = 256 (FullRow), 192(Square) and 256 transposed (FullCol), plus shared A row-major with K = 192 (the generic
mma()path); all exactagainst the float32 reference;
test_nvf4_mma_block_scale_fragment_a_unrolls_k_atoms_and_packs_scales(FullRow, Square): the generated CUDA hasno K-atom loop and no MMA reads
SFA_shared/SFB_shareddirectly.maint/gemm/gemm_sm120/benchmark_sm120_nvfp4_fragment_a_gemm.py: a small pipelined register-A benchmark (A stagedthrough shared memory into a
(block_M, block_K)fragment, B and row-major scales in shared memory), with--verify(bit-exact against float32) and
--dump-source.Tests
On an RTX PRO 6000 Blackwell (SM120, driver 570 + CUDA 13 forward compatibility), TileLang built from source:
main(7a5f446)test_tilelang_language_nvf4_mma_block_scale.py+test_tilelang_language_gemm_blockscaled.pymainvs this PRbash format.sh --files <changed files>: ruff check and ruff format (v0.16.6) pass; no C++ changed.Benchmarks
Two interleaved rounds per build,
do_bench(mean), TFLOPS. The first two rows use code paths this PR does not touch.mainexamples/gemm_sm120/sm120_nvfp4_blockscaled_gemm.py(full-tile K-major)maint/.../benchmark_sm120_nvfp4_blockscaled_gemm.py(persistent, K-major)maint/.../benchmark_sm120_nvfp4_fragment_a_gemm.py, block 128×128×256, FullRowptxas resource usage for the register-A benchmark kernels (
-O3, sm_120a):main: spill stores / loads, LDL+STL in SASSNot addressed here: with
block_K = 128and row-major shared scales the register-A benchmark does not verify onmaineither (same error before and after this change); it needs a separate look.
Notes for reviewers
a_packed_words=Trueregister fragments for block-scaled MMA) and [SM120] kind::mxf8f6f4 block-scaled MMA: full f8f6f4 operand family, sub-byte TMA producers, and official examples #3099 touch the same files. I'll rebase onto [CUDA] Reject conflicting SM120 scale fragment layouts #3284 once it lands.This change is local to the register-A branch of
lower()and tomma(); a rebase should be mechanical.k + 1's B before atomk's MMAs) was tried as well andleft out: no gain on the benchmark above (FullRow/Square within 1%, FullCol −7%).
Context: #1592 (SM120 NVFP4 GEMM for LLM inference). This is the first of the pieces described there.
Summary
Validation
The PR author reports 143 tests passed and 4 skipped on an RTX PRO 6000 Blackwell. The author also reports bit-identical results against a float32 reference and benchmark gains that vary by shape and layout.
The author notes that register-A with
block_K = 128and row-major shared scales still fails verification on bothmainand this change.