feat(loongarch64): add 8-CPU support for LS3A6000

platform/loongarch64/ls3a6000/board.rs

@@ -19,7 +19,7 @@ use crate::{arch::zone::HvArchZoneConfig, config::*, pci::vpci_dev::VpciDevType}
 
 pub const BOARD_NAME: &str = "ls3a6000";
 
-pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_NCPUS: usize = 8;
 
 pub const ROOT_ZONE_DTB_ADDR: u64 = 0x10000f000;
 pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x200000;

platform/loongarch64/ls3a6000/linker.ld

@@ -1,6 +1,6 @@
 ENTRY(arch_entry)
 BASE_ADDRESS = 0x90000001f0000000;
-CPU_NUM = 4;
+CPU_NUM = 8;
 
 
 SECTIONS

src/arch/loongarch64/cpu.rs

@@ -78,8 +78,9 @@ impl ArchCpu {
             .and_then(|zone| zone.read().phys_to_guest_cpu(physical_cpu))
             .unwrap_or(0);
         info!(
-            "[[CPU virtualization]] CPU{} run@{:#x}",
+            "[[CPU virtualization]] CPU{} guest_cpuid={} run@{:#x}",
             self.get_cpuid(),
+            self.ctx.gcsr_cpuid,
             self.ctx.sepc
         );
         debug!("loongarch64: @{:#x?}", self);

src/arch/loongarch64/ipi.rs

@@ -17,7 +17,7 @@
 use crate::arch::cpu::this_cpu_id;
 use crate::consts::{IPI_EVENT_CLEAR_INJECT_IRQ, IPI_EVENT_SEND_IPI};
 use core::arch::asm;
-use core::ptr::write_volatile;
+use loongArch64::iocsr::{iocsr_write_d, iocsr_write_w};
 use loongArch64::register::ecfg::LineBasedInterrupt;
 use loongArch64::register::*;
 
@@ -41,7 +41,6 @@ pub fn arch_notify_event(cpu_id: u64, sgi_num: u64, event_id: usize, queue_was_e
     }
 }
 
-const MMIO_BASE: usize = 0x8000_0000_1fe0_0000;
 const IOCSR_IPI_STATUS: usize = 0x1000;
 const IOCSR_IPI_ENABLE: usize = 0x1004;
 const IOCSR_IPI_CLEAR: usize = 0x100c;
@@ -101,20 +100,14 @@ pub fn mail_send_percore(data: usize, cpu_id: usize, mailbox_id: usize) {
     val |= cpu_id << 16;
     val |= high << 32;
     // debug!("(mail_send) sending high 32 bits, actual packed value: {:#x}", val);
-    unsafe {
-        // asm!("iocsrwr.d {}, {}", in(reg) val, in(reg) 0x1048);
-        write_volatile(IPI_MMIO_MAIL_SEND as *mut u64, val as u64);
-    }
+    iocsr_write_d(IOCSR_MBUF_SEND, val as u64);
     // send low 32 bits
     val = 1 << 31;
     val |= iocsr_mbuf_send_box_lo(mailbox_id) << 2;
     val |= cpu_id << 16;
     val |= low << 32;
     // debug!("(mail_send) sending low 32 bits, actual packed value: {:#x}", val);
-    unsafe {
-        // asm!("iocsrwr.d {}, {}", in(reg) val, in(reg) 0x1048);
-        write_volatile(IPI_MMIO_MAIL_SEND as *mut u64, val as u64);
-    }
+    iocsr_write_d(IOCSR_MBUF_SEND, val as u64);
 }
 
 fn ffs(a: usize) -> usize {
@@ -132,8 +125,8 @@ fn ffs(a: usize) -> usize {
     i + 1
 }
 
-const IPI_MMIO_IPI_SEND: usize = MMIO_BASE + 0x1040; // 32 bits Write Only
-const IPI_MMIO_MAIL_SEND: usize = MMIO_BASE + 0x1048; // 64 bits Write Only
+const IOCSR_IPI_SEND: usize = 0x1040; // 32 bits Write Only
+const IOCSR_MBUF_SEND: usize = 0x1048; // 64 bits Write Only
 
 #[allow(unused_assignments)]
 pub fn ipi_write_action_percore(cpu_id: usize, _action: usize) {
@@ -152,13 +145,10 @@ pub fn ipi_write_action_percore(cpu_id: usize, _action: usize) {
         val |= irq - 1;
         val |= (cpu_id as u32) << 16;
         debug!(
-            "loongarch64::ipi_write_action writing value {:#x} to MMIO address: {:#x}",
-            val, IPI_MMIO_IPI_SEND
+            "loongarch64::ipi_write_action writing value {:#x} to IOCSR: {:#x}",
+            val, IOCSR_IPI_SEND
         );
-        unsafe {
-            //     asm!("iocsrwr.w {}, {}", in(reg) val, in(reg) 0x1040);
-            write_volatile(IPI_MMIO_IPI_SEND as *mut u32, val);
-        }
+        iocsr_write_w(IOCSR_IPI_SEND, val);
         debug!(
             "loongarch64::ipi_write_action sent irq: {} to cpu: {} !",
             irq, cpu_id

src/arch/loongarch64/zone.rs

@@ -14,7 +14,7 @@
 // Authors:
 //      Yulong Han <wheatfox17@icloud.com>
 //
-use crate::device::irqchip::ls7a2000::chip::get_extioi_sr;
+use crate::device::irqchip::ls7a2000::chip::eio_core_isr_mmio_base;
 use crate::{
     arch::{
         cpu::this_cpu_id, ipi::SMP_BOOT_CPU, trap::GLOBAL_TRAP_CONTEXT_HELPER_PER_CPU,
@@ -535,20 +535,13 @@ fn handle_uart_mmio(mmio: &mut MMIOAccess, base_addr: usize) -> HvResult {
 }
 
 fn handle_extioi_status_mmio(mmio: &mut MMIOAccess, base_addr: usize, size: usize) -> HvResult {
-    // first dump all 256 SR regs
-    let extioi_sr = get_extioi_sr();
-    debug!("extioi_sr: {}", extioi_sr);
-
-    // write 0 to clear, so all SR regs are RW
-    // since nonroot runs on cpu2(for example), but it still thinks it's on cpu0, and read SR regs from cpu0
-    // we need to return the correct SR regs to nonroot according to this cpu id
-    let this_cpu_id = this_cpu_id();
-    let target_cpu_sr_start = EXTIOI_SR_CORE_BASE + this_cpu_id * 0x100;
-    let guest_fake_cpu_id = (mmio.address - offset(EXTIOI_SR_CORE_BASE)) / 0x100;
-    let guest_cpu_sr_start = EXTIOI_SR_CORE_BASE + guest_fake_cpu_id * 0x100;
-    let compensation_offset = target_cpu_sr_start - guest_cpu_sr_start;
-    mmio.address += compensation_offset; // since inside each cpu's SR regs region, the "inner offset" should be retained!
-    mmio_perform_access(BASE_ADDR, mmio); // 1fe0_0000, do not use anything else - wheatfox
+    // IOCSR 0x1800 refers to the executing CPU's ISR. CPU4 starts at
+    // node1 + 0x1800 (0x1fe11800), not node0 + 0x1c00 (the route table).
+    let register_offset = (mmio.address - offset(EXTIOI_SR_CORE_BASE)) % 0x100;
+    let original_address = mmio.address;
+    mmio.address = register_offset;
+    mmio_perform_access(eio_core_isr_mmio_base(this_cpu_id()), mmio);
+    mmio.address = original_address;
     Ok(())
 }