feat: flag audit flip-wave — RV shift-fold / dead-frame / uxth (evidence-gated)

[avrabe]

#242 hub lane D — three flag audits with evidence gates; all three flipped default-on.

Per-flag verdict

1. SYNTH_RV_SHIFT_FOLD — FLIPPED (gale's discrepancy confirmed)

True prior default: OFF (env::var_os(..).is_some() opt-in in synth-backend-riscv/src/selector.rs). gale was right (#242 comment 2026-07-03) — the prior lane's "v0.11.x folds default-on" belief conflated this with the ARM SYNTH_NO_IMM_SHIFT_FOLD imm-shift fold (default-on since v0.15.0), a different flag on a different backend.

• Corpus sweep (RV32, --relocatable, 143 function comparisons): 0 grow / 20 shrink — control_step 492→484 (−8 B, exactly gale's esp32c3 number), flat_flight 732→696 (−36), flight_seam controller_step 452→416 (−36), call_6_7args −20/−24.
• shift_fold_riscv_differential.py: 21/21 vs wasmtime, .text 168→148 B, 5 folds — PASS on new default bytes.
• RV32 frozen anchor re-pinned control_step 6ac5d7f9…/484 (was 780e427a…/492); signed_div_const byte-identical (fold-inert). Escape hatch SYNTH_RV_SHIFT_FOLD=0 CI-gated to restore the pre-flip bytes; the older SYNTH_RV_CMP_SELECT=0 hatch gained the composing opt-out.

2. SYNTH_DEAD_FRAME_ELIM (ARM, VCR-RA-002 #390) — FLIPPED

True prior default: OFF (is_ok() opt-in in arm_backend.rs).

• Corpus sweep (both ARM paths — optimized + --relocatable/direct; path-agnostic post-pass): 0 grow / 58 shrink — flight_seam controller_step 250→242 (−8), filter_step 180→168 (−12), native_pointer frame_roundtrip 46→34, leaf_caller_saved leaf3 36→28.
• leaf_dead_frame_differential.py: 10/10 off==on==wasmtime, frame elided 36→28 B — PASS.
• ARM anchors re-pinned: flight_seam 92fd6863…/706 (was 726), flight_seam_flat 660c3fbc…/846 (was 866). SYNTH_DEAD_FRAME_ELIM=0 alone restores the exact prior goldens (CI-gated; the sibling uxth lever is inert on these fixtures).

3. SYNTH_UXTH_FOLD (ARM, #428) — FLIPPED

True prior default: OFF (is_ok() opt-in).

• Corpus sweep (both ARM paths): 0 grow / 13 shrink — control_step_decide 300→294 (−6), uxth_fold pack 36→24 (−12, two folds), gust_mix family −6 each.
• uxth_fold_differential.py: 7/7 off==on==wasmtime — PASS.
• ARM anchor re-pinned: control_step d0907e02…/294 (was 300). SYNTH_UXTH_FOLD=0 alone restores the prior golden (CI-gated; dead-frame inert on control_step).

Combined ARM sweep is exactly additive (71 = 58 + 13): no lever interaction. The #601 local-promo HOLD precedent did not trigger — no function grew anywhere.

Refreeze ritual

Execution differentials re-ran green on the new default bytes BEFORE any golden was pinned. Full scripts/repro/*_differential.py sweep (56 scripts): 55 PASS — 3 initially failed on missing external inputs (call_indirect_594/597 ELFs regenerated per script header, wake_path gist fetched) then passed; sret_decide is a pre-existing, flip-neutral harness discrepancy (script needs an externally supplied ELF with an undocumented invocation; with --native-pointer-abi it runs but vector (3,8,8) mismatches — and the fixture's bytes are byte-identical default vs opt-out, so not this wave's doing; worth its own follow-up issue).

Gates

• cargo test -p synth-synthesis -p synth-backend-riscv -p synth-cli (+ -p synth-backend): 1526 passed / 0 failed — includes the new flag_flip_wave_242.rs per-flag no-grow corpus gates, the re-pinned frozen anchors, and the three new escape-hatch gates.
• Older escape hatches (stack-fwd, spill-realloc, const-CSE, rv32-cmp-select) gained the composing new-lever opt-outs (the documented composition pattern) and still restore their exact pinned bytes.
• RV selector unit tests reworked: the default-shape test now pins the FOLDED default; the fold-mechanism tests drive fold_const_shift on hand-built unfolded streams (coverage independent of the wiring).
• cargo fmt --check clean; clippy -D warnings clean on all touched crates.

🤖 Generated with Claude Code

[codecov]

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