rdl: generate SoC-control regs + memory map from SystemRDL#91
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Squashed the migration/framework work (9 commits) into one block for a cleaner history and an easier rebase over the eventual 64-bit revert: - Vendor chimera-sdk as a submodule (sw/deps/chimera-sdk) with a containerized build (scripts/sdk_container.sh, sw/sw.mk: `make chim-sw*`). - pytest+ctest SoC test framework (test/, scripts/sim_runner.sh): per-test run dirs, SIM_TIMEOUT watchdog + per-test overrides, pytest-xdist parallelism, and a pre-optimized vsim snapshot (chim-opt) for parallel-safe batch runs. - Retire the old sw/ layer: remove sw/tests (migrated to the SDK) and sw/lib; keep sw/include + sw/link for the Snitch bootrom (bootrom migration is a TODO). - Switch the Python environment to uv (.python-version, uv.lock; setuptools<81 for reggen's pkg_resources). - Verification docs, TODO.md, and .vscode IntelliSense config. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
chimera_cluster instantiates snitch_cluster directly (not the generated snitch_cluster_wrapper) and enables RVF/RVD/Xssr/Xfrep/XF* per core, but left the FP-subsystem sizing at snitch_cluster's defaults of 0 (NumFPOutstandingLoads/Mem, NumSsrs/NumSsrsMax, SsrRegs/SsrCfgs, NumSequencerInstr/Loops). A zero-sized FP subsystem makes FP offloads fault with an illegal instruction (e.g. the `fsd` in a cluster function prologue) even though double is nominally enabled -- this is the matmul cluster failure. Integrate the missing parameters from the generated wrapper: source the config-derived pieces (Hive, SsrRegs, SsrCfgs, FPUImplementation, AtomicIdWidth) from snitch_cluster_pkg, size the per-core arrays on NrCores (the DMA core is the last one), and set XDivSqrt=0 to match FPUImplementation (no div/sqrt unit) and the wrapper. Chimera's SoC-integration overrides (TCDM/DMA/ICache sizing, external bootrom, Cfg-derived widths, PMA) are kept. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…dl-rawheader - bender.mk: add the `snitch_cluster_wrapper` target so the generated snitch_cluster_pkg (Hive/SsrRegs/SsrCfgs/FPUImplementation) is compiled. - chimera_cluster: import snitch_cluster_pkg for those config parameters. - pyproject/uv.lock: pin peakrdl-rawheader==0.1.3 -- the snitch_cluster version in use relies on the rawheader 0.1 output format (0.2.x changed it). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
snrt is the slowest test (~1305s in RTL now that the cluster FP subsystem is correctly configured and real FP executes); the 1200s cap tripped it. 3000s gives comfortable margin. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Add cfg/rdl/{chimera_addrmap,chimera_soc_regs}.rdl + rdl.mk (`make rdl`),
rendering the SoC memory map and control registers with peakrdl. The top
address map instantiates the snitch_cluster address map shipped by the
snitch_cluster dependency (resolved via `bender path`, Gwaihir-style), so the
generated map contains the real per-cluster internals (TCDM / bootrom /
peripheral-regs / zeromem) instead of an opaque window. Generates
docs/addressmap.md (markdown), the C address-map header and SV/C region headers
into .generated/ (gitignored). A `rdl-regblock` target renders the SoC-control
SV register block (peakrdl regblock) toward retiring the lowRISC reggen.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
- test/conftest.py: tag each parametrized soc_test with the already-declared `host`/`cluster` marker (by name), so `pytest -m host` / `-m cluster` select subsets (10 cluster + 7 host). - .gitignore: ignore build/. - iis-env.sh: run `bender checkout` so a fresh clone is buildable after a single `source iis-env.sh` (bender checkout + uv sync + activate). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…eggen)
Replace the lowRISC reggen SoC-control block with peakrdl regblock output:
- hw/regs/chimera_reg_{pkg,top}.sv are now generated from
cfg/rdl/chimera_soc_regs.rdl (--cpuif apb4-flat --default-reset arst_n) via
`make rdl-regblock`; hw/regs/chimera_regs.hjson removed.
- hw/chimera_top_wrapper.sv: bridge the register bus to APB4 (reg_to_apb) for the
new block and remap every reg2hw.* consumer to the peakrdl hwif_out struct
(arrays reset_cluster / cluster_clk_gate_en / wide_mem_cluster_bypass, and
snitch_configurable_boot_addr).
- chimera.mk: regenerate_soc_regs now runs rdl-regblock; the reggen rules retired.
- rdl.mk: rdl-regblock emits into hw/regs with an SPDX header.
- Bender.yml unchanged (same hw/regs/*.sv paths).
Validated: full rebuild + 17/17 RTL tests pass, including the register-driven
bootAddrConfig / clusterGating / memoryIsland.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Survey of which components describe their registers/address map in SystemRDL and which are folded into the Chimera memory map. Only snitch_cluster ships RDL (integrated); our cheshire fork still uses reggen; the leaf IP has none. Includes a support matrix and the `bender path` -I mechanism for adding a dependency's RDL. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…f sw/include
RDL-feature subset of the chimera-gen work, independent of the chimera-sdk
chimera-gen target:
- rdl.mk: emit the SoC-control C header and add rdl-sdk-headers, which generates
the dependency register headers (cheshire, clint) and the Snitch cluster SW
headers (snitch_cluster_{cfg,addrmap} via the snitch-sdk clustergen +
snitch_cluster_peripheral via reggen) into .generated. cfg/snitch_cluster.hjson
holds chimera's cluster config (5 clusters, host hart 0).
- Snitch bootrom (snitch_startup.c, snitch_bootrom.S) now includes the generated
headers directly and accesses SoC-control registers via the RDL absolute-address
macros + a computed cluster index.
- Remove the hand-maintained sw/include/{offload.h,soc_addr_map.h,regs/soc_ctrl.h}
and the dead linker files sw/link/{memisl.ld,common.ldh}.
- chimera.mk/sw.mk: build the bootrom against .generated (rdl-raw-header +
rdl-sdk-headers), drop the sw/include include paths.
Verified: Snitch cfg/addrmap/peripheral generate correctly (SNRT_CLUSTER_NUM=5)
and both bootrom sources compile+assemble for rv32 (clang). Full make snitch_bootrom
link + snitch_bootrom.sv regen still needs the RISC-V toolchain.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
… workspace - chimera_cluster.sv now instantiates the generated, parameterized snitch_cluster_wrapper (widths, AXI/SRAM struct types, SnitchPMACfg) instead of a hand-coded snitch_cluster parameter block. All cluster parameters come from cfg/chimera.json (SN_CFG in the Makefile), so the config lives in one place and is rendered by `make sn-hw-all`. - Rename the Snitch bootrom module to chimera_snitch_bootrom (chimera.mk gen flag, chimera_top_wrapper instantiation, generated .sv) to avoid a name collision with the snitch_bootrom module shipped by the snitch_cluster dep. - Adopt the bender clone workspace (Bender.yml package_links for cheshire/snitch_cluster/cva6) and drop the patch/vip_snitch_cluster.sv override; the vip TB is now maintained directly in the snitch clone. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
- Resolve RDL_PYTHON as $(CHIM_ROOT)/.venv/bin/python instead of deriving it from $(dir $(PEAKRDL)); the latter yields ./python when PEAKRDL is a bare name on $PATH (e.g. under iis-env), which broke the Snitch cluster SW header generation. - Consolidate variable definitions into labelled sections (Tools / Paths / Snitch cluster SW headers) at the top of the file. - Prefix all targets with chim- (chim-rdl, chim-rdl-markdown, chim-rdl-c-header, chim-rdl-raw-header, chim-rdl-sw-headers, chim-rdl-regblock, chim-rdl-clean) and update the references in chimera.mk and the docs. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Both clustergens now read cfg/chimera.json instead of maintaining a separate cfg/snitch_cluster.hjson: - cfg/chimera.json gains `nr_clusters` and an `icache.sets` alias (the SW schema's name for `ways`) so the snitch-sdk SW clustergen accepts it too. - rdl.mk: SN_CLUSTER_CFG -> cfg/chimera.json. - Remove cfg/snitch_cluster.hjson (the stale snitch default). This also fixes a HW/SW drift: the old hjson had cluster_periph_size=60, so the SW addrmap placed CLUSTER_ZERO_MEM at PERIPH_BASE+0xf000 while the HW wrapper (periph=64) uses +0x10000. Sourcing both from one file keeps them consistent. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Use the snitch_cluster RTL dependency's own generator ($(SN_ROOT)/util/clustergen/clustergen.py) for the SW cfg/addrmap headers instead of the snitch-sdk's separate copy. It reads the same cfg/chimera.json as the RTL wrapper, so the SW headers can never drift from the generated hardware (verified byte-identical output). Only the header .tpl files still come from the snitch-sdk. Add SN_CLUSTERGEN_CMD to centralise the invocation (PYTHONPATH so the script can `import cluster`; -c/-o CLI instead of the sdk copy's --clustercfg/--outdir). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Migrates the SoC-control register block and global memory map to SystemRDL (peakrdl),
retiring reggen. Top of the stack.
Changes
rdl: SystemRDL global memory map (peakrdl) including the real cluster maprdl: generate the SoC-control register block from SystemRDL (retire reggen)docs: RDL support overview across chimera and its dependencieschore: pytest host/cluster markers, ignorebuild/, iis-env bootstrapOwn commits (on top of #90)
ede8c2crdl: SystemRDL global memory map (peakrdl) incl. the real cluster map70a4831chore: pytest host/cluster markers, ignore build/, iis-env bootstrap56f6e60rdl: generate the SoC-control register block from SystemRDL (retire reggen)a6f6a37docs: RDL support overview across chimera and its dependencies237f259Update to rebased cheshire36e3e82fix(tests): Increase UART baud rate in simulation