L2l2dtrace

profile/plugin/aie_dtrace/aie_dtrace_metadata.cpp

@@ -15,6 +15,7 @@
 #include "core/common/message.h"
 #include "xdp/profile/database/database.h"
 #include "xdp/profile/database/static_info/aie_util.h"
+#include "xdp/profile/plugin/aie_dtrace/util/aie_dtrace_util.h"
 #include "xdp/profile/plugin/vp_base/profiling_runtime_config.h"
 
 namespace xdp {
@@ -29,6 +30,21 @@ namespace xdp {
     return metrics;
   }
 
+  static constexpr const char* L2L2_TRANSFER_METRIC_SET = "l2_l2_transfer";
+
+  bool settingsRequestL2L2Transfer(const std::vector<std::string>& metricsSettings)
+  {
+    for (const auto& setting : metricsSettings) {
+      std::vector<std::string> parts;
+      boost::split(parts, setting, boost::is_any_of(":"));
+      for (const auto& part : parts) {
+        if (part == L2L2_TRANSFER_METRIC_SET)
+          return true;
+      }
+    }
+    return false;
+  }
+
   AieDtraceMetadata::AieDtraceMetadata(uint64_t deviceID, void* handle)
     : deviceID(deviceID)
     , handle(handle)
@@ -54,9 +70,27 @@ namespace xdp {
             + "' from profiling_runtime_config will be supported in a follow-up.");
       }
       if (ci.mem_tile.has_value() && !ci.mem_tile->empty()) {
-        xrt_core::message::send(severity_level::info, "XRT",
-            "AIE dtrace: mem tile metric '" + *ci.mem_tile
-            + "' from profiling_runtime_config will be supported in a follow-up.");
+        if (*ci.mem_tile == L2L2_TRANSFER_METRIC_SET) {
+          l2L2TransferEnabled = true;
+          xrt_core::message::send(severity_level::info, "XRT",
+              "AIE dtrace: enabling L2-L2 via mem_tile metric '" + *ci.mem_tile
+              + "' from Debug.profiling_runtime_config.");
+        } else {
+          xrt_core::message::send(severity_level::info, "XRT",
+              "AIE dtrace: mem tile metric '" + *ci.mem_tile
+              + "' from profiling_runtime_config will be supported in a follow-up.");
+        }
+      }
+    }
+
+    if (l2L2TransferEnabled) {
+      const auto designPoints = aie::dtrace::parseL2L2DesignPoints(
+          xrt_core::config::get_aie_dtrace_settings_l2_l2_design_points());
+      if (designPoints.empty()) {
+        xrt_core::message::send(severity_level::warning, "XRT",
+            "AIE dtrace: L2-L2 is enabled but AIE_dtrace_settings.l2_l2_design_points is "
+            "empty or invalid (expected {column,row:port} entries). "
+            "L2-L2 counters will not be appended to the CT.");
       }
     }
 
@@ -86,6 +120,8 @@ namespace xdp {
     using boost::property_tree::ptree;
     const std::set<std::string> validSettings {
       "tile_based_interface_tile_metrics",
+      "tile_based_memory_tile_metrics",
+      "l2_l2_design_points",
       "configure_aie_hardware",
       "config_one_partition",
     };
@@ -94,6 +130,12 @@ namespace xdp {
     if (auto val = tree.get_optional<bool>("config_one_partition"))
       configOnePartition = *val;
 
+    l2L2TransferEnabled = false;
+    const std::string memTileSettings =
+        xrt_core::config::get_aie_dtrace_settings_tile_based_memory_tile_metrics();
+    if (!memTileSettings.empty())
+      l2L2TransferEnabled = settingsRequestL2L2Transfer(getSettingsVector(memTileSettings));
+
     for (ptree::iterator pos = tree.begin(); pos != tree.end(); pos++) {
       if (validSettings.find(pos->first) == validSettings.end()) {
         std::stringstream msg;

profile/plugin/aie_dtrace/aie_dtrace_metadata.h

@@ -24,6 +24,7 @@ class AieDtraceMetadata {
     double clockFreqMhz = 0.0;
     void* handle = nullptr;
     bool configOnePartition = false;
+    bool l2L2TransferEnabled = false;
 
     std::vector<std::map<tile_type, std::string>> configMetrics;
     std::map<tile_type, uint8_t> configChannel0;
@@ -49,6 +50,8 @@ class AieDtraceMetadata {
 
     bool isConfigOnePartition() const { return configOnePartition; }
 
+    bool isL2L2Enabled() const { return l2L2TransferEnabled; }
+
     bool aieMetadataEmpty() { return metadataReader == nullptr; }
 
     std::vector<std::string> getSettingsVector(std::string settingsString);

profile/plugin/aie_dtrace/util/aie_dtrace_util.cpp

@@ -5,8 +5,69 @@
 
 #include "xdp/profile/plugin/aie_dtrace/util/aie_dtrace_util.h"
 
+#include "core/common/config_reader.h"
+#include "core/common/message.h"
+
+#include <map>
+#include <mutex>
+#include <regex>
+
 namespace xdp::aie::dtrace {
 
+  namespace {
+    using severity_level = xrt_core::message::severity_level;
+
+    static constexpr unsigned int DEFAULT_COALESCE_RESULT_MEMORY_MB = 256;
+
+    void addPortCounterPair(std::vector<L2L2CounterPoint>& points,
+                            uint8_t column,
+                            uint8_t portIndex,
+                            uint8_t runningCounter,
+                            uint8_t stalledCounter)
+    {
+      L2L2CounterPoint running;
+      running.column = column;
+      running.row = MEM_TILE_ROW_START;
+      running.portIndex = portIndex;
+      running.counterNumber = runningCounter;
+      running.eventType = "running";
+      points.push_back(running);
+
+      L2L2CounterPoint stalled;
+      stalled.column = column;
+      stalled.row = MEM_TILE_ROW_START;
+      stalled.portIndex = portIndex;
+      stalled.counterNumber = stalledCounter;
+      stalled.eventType = "stalled";
+      points.push_back(stalled);
+    }
+
+  } // namespace
+
+  void
+  initDtraceOutputConfig()
+  {
+    static std::once_flag once;
+    std::call_once(once, []() {
+      try {
+        xrt_core::config::detail::set("Debug.dtrace_output_json_format", "true");
+        xrt_core::config::detail::set("Debug.dtrace_coalesce_result", "true");
+        xrt_core::config::detail::set("Debug.dtrace_coalesce_result_memory_mb",
+                                      std::to_string(DEFAULT_COALESCE_RESULT_MEMORY_MB));
+      }
+      catch (const std::exception& e) {
+        xrt_core::message::send(severity_level::warning, "XRT",
+            std::string("AIE dtrace: could not apply default dtrace output settings: ")
+            + e.what());
+        return;
+      }
+
+      xrt_core::message::send(severity_level::info, "XRT",
+          "AIE dtrace: enabled JSON dtrace_dump output with coalesced results "
+          "(dtrace_dump_ctx_<slot>_<timestamp>.json on hw context teardown)");
+    });
+  }
+
   std::map<std::string, std::vector<XAie_Events>>
   getBandwidthInterfaceTileEventSets(int hwGen)
   {
@@ -26,4 +87,81 @@ namespace xdp::aie::dtrace {
     };
   }
 
+  std::vector<L2L2InstrumentPoint> parseL2L2DesignPoints(const std::string& spec)
+  {
+    std::vector<L2L2InstrumentPoint> points;
+    if (spec.empty())
+      return points;
+
+    // Format: {column,row:port} — row is accepted for INI readability only (ignored).
+    static const std::regex pointRegex(R"(\{\s*(\d+)\s*,\s*(\d+)\s*:\s*(\d+)\s*\})");
+    const auto begin = std::sregex_iterator(spec.begin(), spec.end(), pointRegex);
+    const auto end = std::sregex_iterator();
+    for (auto it = begin; it != end; ++it) {
+      try {
+        const unsigned long column = std::stoul((*it)[1].str());
+        const unsigned long dstPort = std::stoul((*it)[3].str());
+        if (column > 255 || (dstPort != 1 && dstPort != 2))
+          continue;
+
+        L2L2InstrumentPoint point;
+        point.column = static_cast<uint8_t>(column);
+        point.dstPort = static_cast<uint8_t>(dstPort);
+        points.push_back(point);
+      }
+      catch (const std::exception&) {
+        continue;
+      }
+    }
+    return points;
+  }
+
+  std::vector<L2L2CounterPoint> getL2L2CounterPoints(
+      uint32_t startCol,
+      uint32_t numCols,
+      const std::vector<L2L2InstrumentPoint>& instrumentPoints)
+  {
+    if (numCols == 0 || instrumentPoints.empty())
+      return {};
+
+    const uint32_t endCol = startCol + numCols;
+    std::vector<L2L2CounterPoint> points;
+    points.reserve(instrumentPoints.size() * 2);
+
+/*=================old hardcoded values==========================
+// Stamp 0 edge (col 1): one dst path -> ctr 0,1 -> PerfCtrl0 only
+addPortCounterPair(points, 1, 2, 0, 1);
+
+// Stamps 1-4 middle (cols 5, 9, 13, 17): two dst paths -> ctr 0-3 -> PerfCtrl0 + PerfCtrl1
+addPortCounterPair(points, 5,  1, 0, 1);
+addPortCounterPair(points, 5,  2, 2, 3);
+addPortCounterPair(points, 9,  1, 0, 1);
+addPortCounterPair(points, 9,  2, 2, 3);
+addPortCounterPair(points, 13, 1, 0, 1);
+addPortCounterPair(points, 13, 2, 2, 3);
+addPortCounterPair(points, 17, 1, 0, 1);
+addPortCounterPair(points, 17, 2, 2, 3);
+// Stamp 5 edge (col 21): one dst path -> ctr 0,1 -> PerfCtrl0 only
+addPortCounterPair(points, 21, 1, 0, 1);
+===============================================================  */
+
+    // Assign counters 0-1 for the first dst path on a tile, 2-3 for the second.
+    std::map<uint8_t, uint8_t> nextCounterByColumn;
+    for (const auto& instrumentPoint : instrumentPoints) {
+      const uint32_t column = instrumentPoint.column;
+      if (column < startCol || column >= endCol)
+        continue;
+
+      uint8_t& nextCounter = nextCounterByColumn[instrumentPoint.column];
+      if (nextCounter >= L2L2_MAX_DST_PATHS_PER_COLUMN * 2)
+        continue;
+
+      addPortCounterPair(points, instrumentPoint.column, instrumentPoint.dstPort,
+                         nextCounter, static_cast<uint8_t>(nextCounter + 1));
+      nextCounter = static_cast<uint8_t>(nextCounter + 2);
+    }
+
+    return points;
+  }
+
 } // namespace xdp::aie::dtrace

profile/plugin/aie_dtrace/util/aie_dtrace_util.h

@@ -4,6 +4,7 @@
 #ifndef AIE_DTRACE_UTIL_DOT_H
 #define AIE_DTRACE_UTIL_DOT_H
 
+#include <cstdint>
 #include <map>
 #include <string>
 #include <vector>
@@ -17,6 +18,44 @@ namespace xdp::aie::dtrace {
   // Shim bandwidth metric sets used for Debug.aie_dtrace (not part of standard aie_profile ini).
   std::map<std::string, std::vector<XAie_Events>> getBandwidthInterfaceTileEventSets(int hwGen);
 
+  // ===========================L2L2 transfer metrics ==========================================
+
+  // Inter-stamp memtile halo dst paths; design points come from xrt.ini.
+  // Max dst halo paths per memtile column (4 perf counters, running+stalled per path).
+  static constexpr uint8_t L2L2_MAX_DST_PATHS_PER_COLUMN = 2;
+  // Memtile row 0 (absolute array row 1; row 0 = shim/interface tile).
+  static constexpr uint8_t MEM_TILE_ROW_START = 1;
+
+  struct L2L2InstrumentPoint {
+    uint8_t column = 0;
+    uint8_t dstPort = 1;
+  };
+
+  // One perf counter at a memtile dst halo path (running or stalled).
+  struct L2L2CounterPoint {
+    uint8_t column = 0;
+    uint8_t row = 0;
+    uint8_t portIndex = 1;       // halo dst port (1 = from left neighbor, 2 = from right)
+    uint8_t counterNumber = 0;   // memtile perf counter 0-3 on this tile
+    std::string eventType;         // "running" or "stalled"
+  };
+
+  // Parses AIE_dtrace_settings.l2_l2_design_points, e.g. "{1,1:2},{5,1:1},{5,1:2}".
+  // INI uses {column,row:port} for readability; row is ignored — counters use MEM_TILE_ROW_START.
+  std::vector<L2L2InstrumentPoint> parseL2L2DesignPoints(const std::string& spec);
+
+  // Builds running+stalled counter pairs from xrt.ini design points within the partition.
+  std::vector<L2L2CounterPoint> getL2L2CounterPoints(
+      uint32_t startCol,
+      uint32_t numCols,
+      const std::vector<L2L2InstrumentPoint>& instrumentPoints);
+
+  // ========================================================================================
+
+  // Enable JSON dtrace_dump output with coalesced results by default.
+  // Must run before XRT creates the first dtrace module (config keys lock on first read).
+  void initDtraceOutputConfig();
+
 } // namespace xdp::aie::dtrace
 
 #endif