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release: v0.4.2 - #19

Merged

ktok07b6 merged 225 commits into

mainfrom

devel

Mar 29, 2026

Merged

release: v0.4.2#19
ktok07b6 merged 225 commits into
mainfrom
devel

Commits on Mar 13, 2026
- fix: address v0.4.1 review feedback items
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  71acfab
- refactor: replace IR.is_a() with isinstance() across compiler
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- refactor: introduce match statements for IR type dispatch
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- refactor: additional match statement conversions
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- refactor: decouple usedef from Scope, each pass builds its own
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- refactor: rename IRParser to IRReader, add IRWriter
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- test: add dominator and liveness tests
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Commits on Mar 14, 2026
- feat: add pydantic IR model classes (ir_model.py)
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Commits on Mar 16, 2026
Commits on Mar 17, 2026
Commits on Mar 18, 2026
Commits on Mar 19, 2026
Commits on Mar 20, 2026
- refactor: object.__setattr__ → model_copy in IR transformers (Phase 2-2 partial)
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- refactor: Phi.reorder_args to functional model_copy style
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- refactor: scope.py/ir.py setattr→model_copy (Phase 2-2)
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- refactor: inlineopt.py setattr→model_copy (Phase 2-2)
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- refactor: remove _StmsVisitor/_StmsTransformer, use IrVisitor/IrTransformer
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- test: inlineopt coverage 72% → 90%
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- refactor: inlineopt.py
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- refactor: typeprop.py/portconverter.py setattr→model_copy (Phase 2-2)
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- refactor: split TypeSpecializer into 2-pass functional architecture
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- test: typeprop coverage
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- refactor: Array.items list→tuple immutable
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- refactor: MStm.stms list→tuple immutable
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- refactor: add Ir.subst() and migrate replace→subst in transformers
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- refactor: migrate remaining replace→subst in usedef-linked call sites
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- refactor: remove Ir.replace() in-place mutation method
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- test: add ObjectTransformer unit tests
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- refactor: Phi.args/ps list→tuple immutable
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- refactor: PolyOp.values list→tuple, add list guard asserts in Ir
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- refactor: add type hints to ahdl/ and ir/ base layers (pyright 0 errors in ahdl/)
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  249ac14
- refactor: add type hints to ir/ analysis/scheduling/types layers
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  38dbd55
- fix: constopt worklist identity dedup and stale phi guard
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  b161cc1
- refactor: add pyright type hints to ir/ and transformers/ (0 errors)
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Commits on Mar 21, 2026
Commits on Mar 22, 2026
Commits on Mar 23, 2026
Commits on Mar 24, 2026
Commits on Mar 25, 2026
- test: add scope-level roundtrip tests for IrWriter/IrReader
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- feat(csim): add package skeleton and runtime_template.h
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- feat(csim): signal ID assignment for flat buffer layout
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- feat(csim): emit #define signal ID macros
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- feat(csim): expression visitors (CONST, VAR, OP, IF_EXP)
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- feat(csim): SUBSCRIPT, MEMVAR, FUNCALL, SYMBOL visitors
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- feat(csim): MOVE, ASSIGN, CONNECT statement visitors
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- feat(csim): IF, CASE, BLOCK, SEQ control flow visitors
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- feat(csim): EVENT_TASK, FUNCTION, PROCCALL, no-op and fallback visitors
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- feat(csim): generate() produces complete C source
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- feat(csim): CModelEvaluator with zero-copy shared buffer
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- feat(csim): CSimulatorModelBuilder with gcc compile and MD5 cache
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- feat(csim): add use_csim flag to Simulator with fallback
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- test(csim): end-to-end integration test with expr01
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- fix(csim): sanitize signal names for C identifiers and include ROM signals
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- feat: flatten sub-scope signals in AHDL-to-C transpiler
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- feat(csim): sub-scope flattening, initial value loading, port sync
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- revert(csim): remove port sync that caused simulation hangs
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- feat(csim): add CBufferSignal class for zero-copy port access
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- feat(csim): bind model ports to C buffer via CBufferSignal
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- feat(csim): restore Reg initial value loading into C buffer
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- test(csim): add E2E port sync test via CBufferSignal
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- feat(csim): add USE_CSIM env var for csim toggle
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- fix(csim): mask Invert result to operand width in C code generation
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  cc1eddd
- fix(csim): bind sub-model ports (Handshake/Channel) to C buffer
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- feat(csim): add --csim/--no-csim flags to simu.py
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- test(csim): add regression tests for Invert mask and sub-model port binding
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  a0684cd
- fix(csim): sign-extend masked values for signed signals
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- fix(csim): defer input port writes to match Python Reg double-buffering
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- fix(csim): flush deferred inputs after eval_tasks, not before
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  dc188e3
- fix(csim): fix 7 csim-specific simulation failures
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  d6c8411
- feat(csim): enable csim by default (USE_CSIM=1)
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  27cd0f9
- refactor: use decl-count-based iteration limit for eval_decls
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  9464230
- feat(csim): use CC env var for C compiler selection
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  947be30
- feat(csim): topological sort for eval_decls to reduce convergence iterations
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  be8f545
- feat(csim): separated buffer layout and memcpy-based update_regs
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Commits on Mar 26, 2026
Commits on Mar 27, 2026
Commits on Mar 28, 2026
Commits on Mar 29, 2026
- release: v0.4.2
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  committed
  110ed06

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