Repository navigation
Debug spec v1.0 implementation - #1590
Open
JacobPease wants to merge 251 commits into
Open
JacobPease wants to merge 251 commits into
JacobPease wants to merge 251 commits into
Conversation
…mentation. These implementations will look less like how the JTAG spec mandates it and more like what the Debug spec says it should be.
…on of the Debug Transport Module.
update debug header for tap_controller.sv + some comments
…to reset the op when receiving an acknowledgement as to not trigger another transaction.
…e different fields of the registers.
…ased off of a conceptual state machine diagram in the debug specification.
…not supported) when a 64 bit register read is attempted on an rv32 configuration as a known exception. Warrants more investigation. The spec seems pretty vague about this.
… useful comments as part of a code review.
…for each Spike and OpenOCD pair. Works with make --jobs.
…ulation immediately if the file doesn't exist.
Contributor
|
Please pull all the cosmetic spacing changes out of this PR and put them in a different PR to facilitate merging and review of the substantive changes. |
These files were identical to openhwgroup/debug aside from spacing (e.g. `begin : name` vs `begin:name`). Restoring them keeps the debug-spec work focused on substantive changes.
…s in wallypipelinedcore.sv. Fixed so that it works for 32 bit and 64 bit configurations in both Questasim and Verilator.
… top of the file.
…s at the PC value stored in DPC. The writeback stage is allowed to commit it's instruction, so the pipeline is clear when halted, allowing for the debugger to make changes to the register file in between instruction boundaries cleanly. Halting and flushing now target the memory stage in the hazard unit instead of the WriteBack stage.
…anges." This reverts commit 69d0339.
…rther optimizations needed for the critical path and for proper flushing. All current tests pass.
…greatly simplifying logic.
…ng and resuming. If a debug implementation does not correctly manage pipeline state, certain registers will have old values despite being written to with an Abstract Access Register command.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
4 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This pull request contains an early stage implementation of the Debug Specification. It has the basic features of halting, resuming, resetting, halting on reset, and reading GPRs, CSRs, and FPRs. In it's current state it provides a framework with which we can implement more complicated features, like stepping and going into debug mode on ebreaks in various privilege modes. Inside
docs/debug/wallydebug.mdis a list of features already implemented and features that are going to be implemented.This PR also contains a new method of Verification for the Debug module. Since the Debug module is driven by commands sent over a JTAG interface, separate testvectors must drive the JTAG pins while Wally executes instructions. To accomplish this, a test building framework was developed taking advantage of the features of Spike and the RISC-V variant of OpenOCD which can be found at this repo: riscv-openocd
First we write assembly tests for Spike and we write Tcl scripts to drive OpenOCD. We then run these two programs together as separate processes and connect OpenOCD to Spike's remote bitbang interface. The Tcl commands drive the JTAG pins and allows the RISC-V code, which has certain stopping points in it, to finish executing, ending the test. OpenOCD is configured to output a log of all Debug Module Interface commands it writes over the JTAG interface. This log is scraped for testvectors and saved to a file.
When we run
wsimwith a configuration withDEBUG_SUPPORTEDset high, the testbenches Debugger module is driven with the testvectors generated using OpenOCD and Spike. Several features have been verified using this method.To build and run the debug tests, run the following commands starting in the cvw root directory:
In addition to remaining features to be added, there's room for other improvements and discussion on how to optimally modify the current setup. There are currently only tests written for the
rv64gcconfiguration with Debug supported. Additionally, implementing Imperas support requires thatwsimand the testbench be expanded to take two testvector references when doing single tests on a single elf file and a Debugger testvector file, though thervviinterface to the DMI is simple and easy to add to the testbench. ThisrvviDMI interface is serial interface agnostic and only requires that we connect the DMI signals.