[fengpengboa]

Integrate the RISC-V vector (RVV 1.0) backend from mlkem-native v2.0.0 into liboqs, following the existing x86_64 (AVX2) / aarch64 (NEON) variant pattern. Measurements on K3 hardware show a 44%–61% speedup across keygen, encaps, and decaps, with automatic runtime detection and full C fallback on non-RVV cores. Related to #2580

• Vendored per-parameter-set copies (512/768/1024) carrying the upstream native/riscv64 backend; config_riscv64.h derived from config_aarch64.h (namespace-only).
• Build registration gated on GCC >= 14.1 / Clang >= 17 (minimum for complete RVV 1.0 intrinsics); targets compiled with -march=rv64gcv.
• Runtime detection: HWCAP_ISA_V via getauxval() + VLEN >= 256 check; per-API dispatch falls back to C when RVV is unavailable, so non-RISC-V platforms and pre-RVV cores are unaffected.
• ALGORITHMS.md platform column updated with RISC-V (RVV).

Verified on K3 hardware (RVV 1.0, VLEN=256，gcc15.2):

ML-KEM-512	baseline	RVV	RVV/baseline
keygen	22800	32990	144.69%
encaps	18967	28725	151.45%
decaps	15864	25653	161.71%

ML-KEM-768	baseline	RVV	RVV/baseline
keygen	14281	20201	141.45%
encaps	12648	18807	148.70%
decaps	10720	16639	155.21%

ML-KEM-1024	baseline	RVV	RVV/baseline
keygen	9785	13867	141.72
encaps	8741	12905	147.64%
decaps	7597	11562	152.19%