🎨 Support alias-safe repeated qubit loads - #1987
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Just two small requests for changes. Otherwise, this should be good to go.
Treat QC qubit loads as register provenance and materialize QCO values only around each quantum operation. Carry complete QTensor state through structured control flow and restrict QTensor canonicalization to alias-safe local rewrites. Assisted-by: GPT-5.6 via Codex
Allocate non-scalar declarations as storage and load checked static or dynamic references at each quantum use. Remove width-expanded quantum dispatch while preserving alias assertions and classical emission guards. Assisted-by: GPT-5.6 via Codex
Add the direct declarations required by clang-tidy and keep local test helpers at internal linkage. Update the Python MLIR fixture to the canonical load-at-use ordering produced by the alias-safe pipeline. Assisted-by: GPT-5.6 via Codex
Use MLIR region capture utilities, reject provably duplicate simultaneous operands, and remove dead modifier register state. Strengthen structured tensor linearity tests and normalize translation fixtures through the production conversion pipeline. Clarify eager versus storage-only builder APIs and stop treating register loads as standalone allocations. Assisted-by: GPT-5.6 via Codex
Count and emit only potentially aliasing register pairs instead of scanning every pair. Use LLVM dense containers for barrier uniqueness, reject unavoidable whole-register aliases early, and cover large static barriers without width-quadratic work. Assisted-by: GPT-5.6 via Codex
Record the exhaustive remediation rounds, current-base integration, final validation, MLIR design decisions, and the remaining exact-head review step in the living ExecPlan. Assisted-by: GPT-5.6 via Codex
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Description
Make repeated and runtime-indexed qubit register loads alias-safe without relying
on CSE for correctness.
The QC-to-QCO conversion now treats qubit
memref.loadoperations as accessprovenance. It materializes register-backed qubits immediately around each
quantum operation, commits results in reverse extraction order, and carries
complete QTensor values through structured control flow. Local QTensor
canonicalizations only fold accesses whose indices MLIR proves equal.
The typed OpenQASM frontend now allocates non-scalar qubit declarations as
storage and emits checked point-of-use loads. Quantum register access therefore
no longer expands into width-dependent
scf.index_switchdispatch. Exactduplicate simultaneous operands are rejected semantically, while potentially
aliasing dynamic gate and barrier operands receive runtime assertions.
Fixes #1893
Validation
configured as skipped.
round-trip suites pass.
mqt-ccsuccessfully emits QC, QCO, and Adaptive QIR for dynamic gate,modifier, measurement, reset, and barrier accesses.
issues.
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