feat(MODEL-MM-QWEN4-EXP): W2 — the hashed n-gram index and the PLE dilated conv, the two components with no vLLM op

.agents/specs/qwen4-exp-flash-next.md

@@ -737,6 +737,40 @@ change that makes any arm reachable, not later.
 - GGUF k-quant arms, including authoring the `qwen4_exp` architecture on our side,
   and the statement that no llama.cpp oracle exists for them.
 - MTP depth > 1.
+- **W2 (#1987) lands UNREACHED, by AGENTS.md "Nothing lands dead".**
+  `src/vllm/model_executor/models/qwen4_exp_ple.{h,cpp}` is a host reference
+  for the n-gram hashed embedding and the PLE dilated depthwise conv. No
+  production entry point calls it: `qwen4_exp` has no registry entry, no
+  loader and no `ModelRegistry::Forward` arm until W5 assembles the model.
+  The wiring is owned by row `MODEL-MM-QWEN4-EXP` (W5) and tracked by
+  campaign issue [#1978](https://github.com/mudler/vllm.cpp/issues/1978).
+  Also owed from that wave: the batched device arm (the host signatures are
+  per-sequence precisely so it drops in), the 128-shard NUMERIC table
+  reassembly, and the prefix-caching decision for a conv state written by a
+  chunked prefill shorter than 9 columns, which `## Design` records as
+  AMBIGUOUS and not resolvable from upstream.
+- **W2's float path has never been compared at MODEL WIDTH, and that is the one
+  gap its own gate cannot close.** `tests/vllm/models/test_qwen4_exp_ple.cpp`
+  runs at `hidden_size = 8`, `hc_count = 2`, `heads_per_ngram = 2`,
+  `ngram_vocab_size_base = 20`. Only the multipliers, the prime head sizes and
+  the offsets are pinned at the released config, and those are INTEGERS, where
+  width cannot change an answer. Everything float — the grouped RMSNorm, the
+  gate reduction that is 2560 wide in the real model, the 10240-channel dilated
+  conv — is gated at width 16 with 8-wide groups. Every structural mutation in
+  the W2 table dies there by orders of magnitude, so the instrument is sound for
+  structure; a REDUCTION-ORDER difference at width 2560 is what it cannot see,
+  and it is exactly the class of difference that a device arm introduces.
+  Owed: a first real-width numeric comparison against the lane pin. It must
+  derive a **relative** bound, not reuse W2's absolute `1e-5`. W3's repair on
+  the sibling branch measured the reason: an exact-double evaluation of the
+  oracle's own algorithm for the gated residual already exceeds a 1e-5 absolute
+  bound at model width, because torch runs the reduction in fp32, so an absolute
+  bound at that width tests the accumulator and not the port.
+- The `conv_mask` contract beyond the host arm. W2 gates the masking itself
+  (both tensors, and through the 9-column state), but the PAIRED obligation it
+  documents — a masked position must already carry EOS in `input_ids`, because
+  the hash reads ids and not activations — is a CALLER obligation with no caller
+  yet. W5 owns asserting it where the mask is built.
 - The 1M-token RoPE extension above the native 262144.
 - The non-resident n-gram table on CUDA: the dequantizing gather op and the
   `kEmbeddingTable` keep-quant policy change (Route B), and a measurement of the

CMakeLists.txt

@@ -801,6 +801,7 @@ add_library(vllm STATIC
   src/vllm/model_executor/models/dots3_note_attn.cpp
   src/vllm/model_executor/models/dots3_note_device.cpp
   src/vllm/model_executor/models/dots3_note_registry.cpp
+  src/vllm/model_executor/models/qwen4_exp_ple.cpp
   src/vllm/model_executor/models/laguna_registry.cpp
   src/vllm/model_executor/models/laguna_weights.cpp
   src/vllm/model_executor/models/interfaces.cpp

tests/CMakeLists.txt

@@ -3113,3 +3113,17 @@ foreach(_pc_target
     target_include_directories(${_pc_target} PRIVATE ${CMAKE_SOURCE_DIR}/src)
   endif()
 endforeach()
+
+# Qwen4-Exp (`Qwen4ExpForConditionalGeneration`) W2 -- the hashed n-gram
+# embedding and the PLE dilated depthwise conv (#1987, campaign #1978,
+# .agents/specs/qwen4-exp-flash-next.md). These are the ONLY two components of
+# the model with NO vLLM op, confirmed by a negative search rather than an
+# unfound one, so transformers v5.16.0 -- this row's accepted lane pin -- is the
+# sole oracle and the goldens beside this file were produced by EXECUTING
+# upstream's own bytes. The spec admits no token gate for this row until an arm
+# runs (nothing published fits any fleet device), so G0 component goldens are
+# the whole instrument. CPU-only, no checkpoint, no GPU, no speed claim.
+vllm_cpp_add_test(test_qwen4_exp_ple vllm/models/test_qwen4_exp_ple.cpp)
+# qwen4_exp_ple.h is a MODEL-PRIVATE header under src/, same arrangement as the
+# dots3-note gates above: W2 ships nothing on the public ABI.
+target_include_directories(test_qwen4_exp_ple PRIVATE ${CMAKE_SOURCE_DIR}/src)