feat(MODEL-MM-QWEN4-EXP): W1 — resolve and validate the qwen4_exp config, register the arch, and refuse by name

.agents/claims/CLAIM-MODEL-MM-QWEN4-EXP-W1.md

@@ -0,0 +1,5 @@
+# CLAIM-MODEL-MM-QWEN4-EXP-W1
+
+| Claim | Row IDs | Agent | Worktree / remote dir | Branch | Owned scope | State | Last update |
+|---|---|---|---|---|---|---|---|
+| `CLAIM-MODEL-MM-QWEN4-EXP-W1` | `MODEL-MM-qwen4-exp-qwen4-exp-for-conditional-generation` (`ACTIVE`) | Claude Code (opus-5), fresh implementer repairing a review — the review was written by a different agent and the code by a third | isolated worktree `/home/mudler/_git/vllm.cpp-q4w1`; CPU-only Debug build, NO GPU, NO checkpoint, NO benchmark. One download: `transformers` 5.16.0 into a scratch venv, which is what makes the config layer of this row oracle-gated at all | `row/MODEL-MM-QWEN4-EXP-W1`, PR [#1986](https://github.com/mudler/vllm.cpp/pull/1986), issue [#1981](https://github.com/mudler/vllm.cpp/issues/1981) under campaign [#1978](https://github.com/mudler/vllm.cpp/issues/1978) | Owns ONLY the W1 config surface: `src/vllm/model_executor/models/qwen4_exp.{h,cpp}`, `src/vllm/model_executor/models/qwen4_exp_registry.cpp`, `tests/vllm/models/test_qwen4_exp_scaffold.cpp` and its fixture, the `qwen4_exp` rows in `docs/FEATURES.md` and `.agents/model-matrix.md`, and `.agents/specs/qwen4-exp-flash-next.md`. EXCLUDES the shared `HfConfig` reader, whose `partial_rotary_factor` semantics this row now DEPENDS on rather than duplicates; EXCLUDES every other registered architecture; EXCLUDES the loader, forward, KV-cache spec and GGUF arm, which W2-W6 owe and which this row only refuses by name | `ACTIVE` | 2026-08-26 — W1 landed at `a4c144fb6`, failed a fresh review, and this claim carries the repair. The deciding finding retracted an "inherited 0.25" `partial_rotary_factor` default that does not exist at the pin; four more defaults were wrong in the same direction, and three production refusals (the `parse_config` hook, the forward, the GGUF arm) could each be deleted without a red. The row's product is a refusal BOUNDARY and it is now measured rather than described: a 39-case two-direction sweep against a running `transformers` 5.16.0 (it imports without torch, so `validate_architecture` executes) agrees on 35 and differs on 4, every difference being a local guard STRICTER than upstream. All 15 upstream rejections are tabulated against their upstream line in the spec's `## The refusal boundary`. `test_qwen4_exp_scaffold` 7 cases/151 assertions to 12/294 |

CMakeLists.txt

@@ -800,6 +800,8 @@ add_library(vllm STATIC
   src/vllm/model_executor/models/dots3_note_attn.cpp
   src/vllm/model_executor/models/dots3_note_device.cpp
   src/vllm/model_executor/models/dots3_note_registry.cpp
+  src/vllm/model_executor/models/qwen4_exp.cpp
+  src/vllm/model_executor/models/qwen4_exp_registry.cpp
   src/vllm/model_executor/models/laguna_registry.cpp
   src/vllm/model_executor/models/laguna_weights.cpp
   src/vllm/model_executor/models/interfaces.cpp

docs/FEATURES.md

@@ -124,6 +124,7 @@ speed-pending, which [BENCHMARKS.md](BENCHMARKS.md) tracks.
 |---|---|---|---|
 | `Qwen3_5ForConditionalGeneration` | Qwen3.6-27B NVFP4 (`unsloth` @`890bdef7`, `nvidia` @`0893e160`); Qwen3.5-4B BF16; **Qwen3.8-27B BF16** @`1d4bf0f2` | 27B strict 235/235 text + 32/32 image/video; 4B cached 3/3; Qwen3.8-27B 4/7 strict, 3 exact fp32 ties in band (#915) | `unsloth` 27B at/above vLLM, ModelOpt 0.85x; 4B 1.021x; 3.8-27B c4 **0.963x**, c1/c8 absolutes (#915). Loads BF16/per-tensor FP8/NVFP4 (CT+ModelOpt); `modelopt_mixed` FP8 tower NATIVE (#164), GDN qkvz merged. CUDA/CPU |
 | `Qwen3_5MoeForConditionalGeneration` | Qwen3.6-35B-A3B (NVFP4 text; published BF16 text + vision tower) | NVFP4 strict 315/315 vs vLLM 0.25.0; published BF16 6/7 prompts strict 16/16 vs the pin, 7th an exact tie (#910). Image/video IMPLEMENTED, NOT GATED (#891): the tower loads and runs, mm gate OWED | gate model: 0.93x to 1.03x grid; NO BF16 or mm speed claim |
+| `Qwen4ExpForConditionalGeneration` | none — **REGISTERED, NOT LOADABLE** (W1, [#1981](https://github.com/mudler/vllm.cpp/issues/1981)) | **CONFIG LAYER GATED; nothing above it is.** The config resolves and validates against a RUNNING transformers 5.16.0 oracle (it imports without torch, so `validate_architecture` executes): a 39-case two-direction sweep agrees on 35 and differs on 4, all four being local guards stricter than upstream, never looser. All 15 upstream `validate_architecture` rejections are implemented and tabulated against their upstream line. The loader, the forward and the KV-cache spec all REFUSE BY NAME, each naming the wave that owes it. vLLM implements `qwen4_exp` at NO revision, so the algorithm oracle is transformers **5.16.0** under an accepted lane exception; `gateable = no` because nothing published fits a fleet device — `Qwen/Qwen3.8-Flash-Next` is ~360 GB bf16, ~180 GB FP8, ~128 GB NVFP4 against ~119.6 GiB usable on GB10 | none, and no speed claim is admissible from this row until a token gate exists |
 | `Qwen3_5ForCausalLM`, `Qwen3_5MoeForCausalLM` | none: no text-only Qwen3.5 checkpoint fits this hardware | **NO RUN GATE, OWED.** Gated on `test_qwen3_8_text_only.cpp`; NO token claim. Loader reads stacked BF16 experts (#740) plus BF16 towers, shared expert and `lm_head` (#864), so both published indices satisfy the load plan | not measured |
 | `Qwen3ForCausalLM` | Qwen3 dense 0.6B/1.7B/4B/32B, NVFP4A16 | near-tie strict 16/16 vs vLLM 0.25.0 | c1 every-axis parity, c8 decode residual |
 | `Qwen3MoeForCausalLM` | Qwen3-Coder-30B-A3B | strict 6/6 vs vLLM 0.25.0 | 11/16 grid cells at or above graphed vLLM |