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gate_nvtier: load the all-RAM arm before the paged arm, and declare its real host need - #633
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The paged arm's tier, which the room, advice, footprint and counters clauses read after both arms, kept its RAM arena (about 23.5 GB on the gate plan) mapped while the all-RAM arm loaded. That arm's host need (105.8 GB on the gate plan) does not count the arena, but the host's reading had already lost it, so a 128 GB host refused the load although the arm alone fits. The all-RAM arm now loads first, as the nvtier family gate already orders its arms.
The row declared 92,054,154,240 B, the qwen4exp plan's need, but the gate's all-RAM arm also holds the 14.6 GB residency churn pool and needs 105,818,045,440 B.
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Verdict: CLEAN: The load order removes the retained-arena conflict, and the resource declaration matches the all-RAM load's stated need.
Non-blocking
⚠ Complete gate evidence: crates/gpu-gates/src/bin/gate_nvtier.rs:2002, the PR identifies the upstream base but omits the exact revisions of the two measured builds. It also reports a temporary 5090 card-selection edit. Record the measured revisions alongside that edit and the run output to make the comparison reproducible, as CONTRIBUTING.md requires.
Checked
Duplicates: 0 new functions, types or constants; no dryer pairs supplied. The sibling family gate already loads all-RAM first.
Complexity: crapper flagged no functions; the reorder adds no branches.
Silent failure: 0 added sites; both arm loads still propagate errors.
Tests: assertions unchanged. Restoring paged-first is the reported mutant; it fails at the host-load check on the reported 128 GB host. GPU execution was not repeated here.
Gates: no assertions, bands or pins moved; the host-resource declaration increased. Its sum is 105,818,045,440 B [derived from the listed terms].
Adversarial checks: the all-RAM session drops before the paged load; footprint preparation drops warmed pages; grant children still precede both arms.
Performance: gate load order only; no engine hot path changed.
Escape catalog: no patterns matched.
Notes
dryer did not run. Diagnostics says no changed Rust file is under crates/, although gate_nvtier.rs is changed.
Card check: needs-gpu. This pull request changes crates/gpu-gates/src/bin/gate_nvtier.rs and carries no gate run on a card (CONTRIBUTING's evidence list); a maintainer adds gpu-verified after one.
🔨 Shingler, bloomery's review bot: approves a clean pull request and requests changes on a must-fix (how it works)
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The review is done and the contribution check passed, so I'm merging this. |
gate_nvtier가 all-RAM 팔을 paged 팔보다 먼저 load하도록 순서를 바꾸고, 이 gate의 자원 선언을 실제 필요량으로 고칩니다.
Fixes the
gate_nvtieritem in #524.What and why
gate_nvtierrefused to load its all-RAM arm on a 128 GB class host, although that arm fits there when it loads alone. The gate loaded the paged arm first. That arm's NVMe tier keeps a RAM arena of 23,494,107,136 B alive until the stepunion arms, because the clauses after the two arms read the tier. The host check at the all-RAM arm's load readsMemAvailable, and that arena was already gone from it. On an RTX 5090 machine the refusal read: the host has 102,243,987,456 B available, under the 105,818,045,440 B this load needs.This pull request makes two changes:
crates/gpu-gates/src/bin/gate_nvtier.rsloads the all-RAM arm first, so its host check sees the whole host. The clauses that compare the two arms read only values that do not depend on the order (tokens, digests, split walk, stats).shared/nvtier_family.rsalready loads its all-RAM arm first.tools/gate-batch-resources.tsvdeclaresgate-gpu-nvtierat 105,818,045,440 B, the need the all-RAM arm's load check reports, instead of 92,054,154,240 B. The paged arm loads after it with a smaller need of 5,495,181,312 B plus its 23,494,107,136 B arena, so the all-RAM arm sets the maximum. A comment in the file shows the sum.The model load path is unchanged.
placed_preincrates/gpu/src/model.rsreadshost_available()and checksHostNeed::of(plan, extra).grantonce, before the card upload and before any host set is read. The only earlier allocation is the CUDA context, so the load does not count its own allocations twice. The refusal came from the gate holding an earlier arm's arena, not from the load.Release notes: internal: the nvtier gate loads its all-RAM arm first so it runs wherever that arm fits alone, and its resource row matches that arm's host need
Code shape
shared/nvtier_family.rs.cargo fmtandcargo clippyare clean on what I touched; the lint count did not go up.Duplication found or removed (
path:line): none.What I ran
The pull request is two commits on upstream main
58356c00. Both runs below used the arm-order change; the head differs from the measured build only in comment text and the resource table row.On a Mac:
The gate on an RTX 5090 machine, once with the paged arm first (main's order) and once with the all-RAM arm first (this pull request):
With this pull request every clause passed, including the clauses that compare the two arms (bits, split, floor-serve, counters). At the all-RAM arm's load the gate process held about 144 MiB of anonymous memory and
MemAvailablewas 120,034 MiB. Under main's orderMemAvailableread 97,045 MiB while the paged arm's arena was held.What I ran into
This does not block the pull request.
shared/gate_card.rsopens the real tier by name only on an A6000 or a 3090, which are the cards this gate names, and an RTX 5090 is not among them. To run the gate on the 5090 I added one line during the run,.or(device.name.contains("5090").then_some("5090")), and reverted it afterwards. The plan used the 3090's bytes, and the run printedmove proof card bytes ... PASS. That line is not in this pull request. I did not run the gate on an A6000 or a 3090.Hardware (if the change is for a machine)
nvidia-smiprints this GPU name, driver and CUDA version:The gate ran against
Qwen3.8-Flash-Next-UD-Q4_K_XL. The host has 128 GB class memory (MemAvailable120,328 MiB at the gate's start). The arena of 23,494,107,136 B comes from the gate's plan, which uses the 3090's card bytes.AI help
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