pci_core: introduce DmaTarget to bundle DMA memory and MSI identity#3786
Open
jstarks wants to merge 3 commits into
Open
pci_core: introduce DmaTarget to bundle DMA memory and MSI identity#3786jstarks wants to merge 3 commits into
jstarks wants to merge 3 commits into
Conversation
|
This PR modifies files containing For more on why we check whole files, instead of just diffs, check out the Rustonomicon |
Contributor
There was a problem hiding this comment.
Pull request overview
This PR introduces pci_core::dma::DmaTarget, a new plumbing type that bundles a PCI device’s DMA memory (GuestMemory), MSI identity/routing (MsiTarget), and optional IOMMU-backed per-RID translation factory to keep DMA and MSI requester identity consistent (notably for SR-IOV VFs).
Changes:
- Added
pci_core::dma::DmaTarget(+DmaTargetIommu) and threaded it through PCI device resolution/building to replace separateguest_memory/msi_target(andsoftware_iommu) parameters. - Extended
MsiTargetwithwith_rid()and added range validation so out-of-range RID bus overrides drop/disable MSI delivery rather than using an invalid identity. - Added generic IOMMU support for per-RID translating DMA memory via
iommu_common::TranslatingDmaTargetand updated SMMU/AMD-IOMMU wiring to feed this intoDmaTarget.
Reviewed changes
Copilot reviewed 18 out of 18 changed files in this pull request and generated 2 comments.
Show a summary per file
| File | Description |
|---|---|
| vmm_core/src/device_builder.rs | Switches PCI device resolution to pass DmaTarget instead of separate DMA/MSI inputs. |
| vm/devices/virtio/virtio/src/resolver.rs | Uses input.dma_target to obtain GuestMemory + MsiTarget for virtio PCI devices. |
| vm/devices/storage/nvme/src/tests/controller_tests.rs | Updates NVMe tests to construct/pass DmaTarget. |
| vm/devices/storage/nvme/src/resolver.rs | Updates NVMe resolver to pass DmaTarget into controller construction. |
| vm/devices/storage/nvme/src/pci.rs | Updates NvmeController::new to take &DmaTarget and derive DMA/MSI from it. |
| vm/devices/storage/nvme_test/src/resolver.rs | Updates NVMe fault controller resolver to derive DMA/MSI from DmaTarget. |
| vm/devices/pci/vfio_assigned_device/src/resolver.rs | Switches VFIO assignment checks/MSI wiring to use DmaTarget (software_iommu() + MSI target access). |
| vm/devices/pci/pci_resources/src/lib.rs | Updates resolve parameter struct to carry &DmaTarget instead of separate fields. |
| vm/devices/pci/pci_core/src/msi.rs | Adds with_rid() and validates override bus against assigned bus range; adds tests for new behavior. |
| vm/devices/pci/pci_core/src/lib.rs | Exposes the new dma module. |
| vm/devices/pci/pci_core/src/dma.rs | Adds DmaTarget and the IOMMU factory trait for per-function/RID DMA memory derivation. |
| vm/devices/net/gdma/src/resolver.rs | Updates GDMA resolver to use DmaTarget for DMA/MSI inputs. |
| vm/devices/iommu/smmu/src/shared.rs | Derives Clone for SmmuTranslator to support per-VF factory cloning. |
| vm/devices/iommu/iommu_common/src/lib.rs | Adds per-RID translating GuestMemory and TranslatingDmaTarget implementation of DmaTargetIommu. |
| vm/devices/iommu/amd_iommu/src/lib.rs | Derives Clone for AmdTranslator and adjusts tests/imports for bus range handling. |
| openvmm/openvmm_core/src/worker/dispatch/pcie_wiring.rs | Builds a per-device DmaTarget (optionally IOMMU-backed) as part of PCIe device wiring. |
| openvmm/openvmm_core/src/worker/dispatch.rs | Threads DmaTarget through PCIe device construction and updates VPCI resolve context creation. |
| openhcl/underhill_core/src/worker.rs | Updates Underhill VPCI device build path to create a DmaTarget-based resolve context. |
PCI bus-mastered transactions—DMA reads/writes and MSI interrupts—are both identified by a device's Requester ID. Today those two concerns are plumbed through device construction separately, as a `GuestMemory` and an `MsiTarget`, which makes it easy to hand a device a DMA path and an MSI path that disagree on identity and leaves no single place to derive a per-function identity for SR-IOV virtual functions. This introduces `DmaTarget` in `pci_core`, bundling a device's `GuestMemory`, its `MsiTarget`, and an optional IOMMU factory into one value. `with_devfn` and `with_rid` derive both the DMA and MSI identity for a given function or Requester ID together, so the two cannot drift apart. When an IOMMU is present the factory—implemented by `iommu_common`'s `TranslatingDmaTarget` over the shared `IommuTranslator`— produces per-RID translating `GuestMemory`, and the SMMU and AMD IOMMU wiring both flow through it. `DmaTarget` is threaded through the PCIe device wiring, the device resolvers, and `device_builder`, replacing the separate `guest_memory` and `software_iommu` plumbing. This is groundwork for NVMe SR-IOV, where each virtual function needs a distinct, consistent DMA and MSI identity.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
PCI bus-mastered transactions—DMA reads/writes and MSI interrupts—are both identified by a device's Requester ID. Today those two concerns are plumbed through device construction separately, as a GuestMemory and an MsiTarget, which makes it easy to hand a device a DMA path and an MSI path that disagree on identity and leaves no single place to derive a per-function identity for SR-IOV virtual functions.
This introduces DmaTarget in pci_core, bundling a device's GuestMemory, its MsiTarget, and an optional IOMMU factory into one value. with_devfn and with_rid derive both the DMA and MSI identity for a given function or Requester ID together, so the two cannot drift apart. When an IOMMU is present the factory—implemented by iommu_common's TranslatingDmaTarget over the shared IommuTranslator—produces per-RID translating GuestMemory, and the SMMU and AMD IOMMU wiring both flow through it.
DmaTarget is threaded through the PCIe device wiring, the device resolvers, and device_builder, replacing the separate guest_memory and software_iommu plumbing. This is groundwork for NVMe SR-IOV, where each virtual function needs a distinct, consistent DMA and MSI identity.