pci_core: make 64bit BARs prefetchable#3775
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Pull request overview
This PR aims to ensure emulated 64-bit PCI BARs are treated as prefetchable so platform/firmware BAR placement will put them into the MMIO-high region, and updates BAR write handling to preserve BAR attribute bits.
Changes:
- Marks 64-bit BAR masks as
prefetchablewhen constructing config-space BAR masks. - Preserves BAR attribute bits (64-bit + prefetchable) when the guest writes BAR values.
jstarks
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jstarks
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Jun 18, 2026
| bar_value = cfg_space::BarEncodingBits::from_bits(bar_value) | ||
| .with_type_64_bit(true) | ||
| .with_type_64_bit(attrs.type_64_bit()) | ||
| .with_prefetchable(attrs.prefetchable()) |
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I agree that 64bit bars don't have to start on an even index, but won't this new logic accidentally interpret the upper 32-bits of the 64bit BAR as encoding bits?
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ie. if there's a 64bit BAR spanning BAR indices 1 and 2, I think it'll interpret the 4 least significant bits of BAR2 as encoding bits, but isn't that wrong because it's an upper-BAR?
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Boot configuration only places 64bit BARs in the MMIO high if the BAR is also marked as prefetchable. Mark all emulated 64bit BARs prefetchable.