Inspect ADIv6 access ports and RP2350 debug components. - #72
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DPv3 banks the DPIDR address and adds the address-width and discovery-base registers needed to locate its access ports. Treating DPIDR as independent of SELECT would return another register after reading a nonzero bank. Select the correct bank for immediate and queued DP reads, expose the DPv3 registers, and model them in the behavioral target. Earlier debug ports and baseline JTAG reject registers they do not implement.
ADIv6 uses aligned AP base addresses and 4 KiB register windows instead of ADIv5 APSEL indices. Reusing an index would select the wrong register. Keep those selectors distinct, check them against the connected DP and its advertised address width, and select both address words when needed. Immediate AP reads and writes retain posted completion and existing recovery. Queued AP operations and MEM-AP acquisition remain ADIv5-only.
ADIv6 MEM-APs place their registers at offset 0xd00. Use that layout inside the existing memory client and accept base-address selectors in armdebug so callers retain the same acquisition and cleanup rules. Share sequential transaction execution with JTAG while retaining packed ADIv5 SWD transfers. Complete each AP operation before advancing, preserve confirmed block prefixes, and keep failed restoration retryable. Reject error modes that could suppress failures the client needs to observe.
An ADIv6 debug port advertises a component tree in its own address space, separate from memory reached through a MEM-AP. Expose a borrowed word reader and decode BASEPTR0/1 so the existing bounded CoreSight walker can discover AP bases without a second ROM parser or a hard-coded scan. Keep raw-access invalidation visible, reject unsupported widths and malformed bases, and leave cleanup with the debug-port owner.
The example previously accepted only an ADIv5 AP index. Add explicit ADIv6 AP-base and DP debug-space selections so the same bounded walker can inspect the advertised AP hierarchy or memory behind a chosen AP. Keep selection and output in the example while the borrowed readers own addressing. Record the RP2350 discovery and memory observations with the commands, cleanup results, and limits of the bench evidence.
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ADIv6 AP selectors checked the debug port's address width, but raw SELECT and SELECT1 writes could still send reserved address bits. Apply the same limit to immediate and queued DP writes before any traffic, while allowing the independent DPBANKSEL field.
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Fixture setup accepted selectors for incompatible or unsupported DP versions and ADIv6 addresses beyond the configured width. The public DAP API could not reach those fixtures despite their successful setup. Validate selectors against the target's DPIDR during fixture setup and updates, and check ADIv6 addresses against its supported address width. DPv3 fixtures require DPIDR1 to be configured first.
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Add DPv3 register access, ADIv6 AP base-address selection, and MEM-AP access through the existing DAP and Arm debug owners. A borrowed debug-space reader composes with the bounded CoreSight walker to discover AP bases. The CoreSight example accepts
-debug-spaceand-ap-baseselections. The existing ADIv5 SWD and baseline JTAG paths remain available.Given an open
armdebug.Connnamedconnection, inspect the DP's advertised hierarchy before acquiring MEM-APs:Select a discovered MEM-AP explicitly. On the exercised RP2350, one is at
0x2000:The caller retains
connectionand closes it after inspection, retrying failed cleanup. Raw debug-space reads can have register-specific effects and invalidate existing MEM-AP clients, so discovery precedes memory acquisition. Neither operation acquires or halts the processor.APSel.Addressnow acceptsuint16. Untyped constants need no change; typed byte offsets migrate as follows:NewAPSelandValuedescribe ADIv5 indices;APAtandBaseAddressdescribe ADIv6 bases. The zero selector remains invalid. DPv3 also exposes DPIDR1, BASEPTR0/1, and SELECT1 through the existing logical register API.Why
ADIv6 uses a debug address space and 4 KiB AP register windows instead of ADIv5 APSEL indices and 256-byte windows. Its discovery root belongs to the DP's address space; a MEM-AP's advertised debug base belongs to target memory. Keeping those spaces explicit lets the existing component reader and ROM walker serve both.
ADIv6 transactions complete each AP operation before sending the next, sharing the sequential execution used by JTAG. ADIv5 SWD retains packed execution. Address-width and architecture checks reject invalid selections before AP requests. If MEM-AP restoration fails, the caller can retry cleanup. DP ERRMODE and MEM-AP modes that suppress or defer errors remain unsupported and are rejected.
Documentation
Update the DAP, architecture, composition, capability, and CoreSight guides, along with the example instructions. Document the address-argument migration, borrowed-reader lifetime, discovery bounds, and the distinction between DP and target-memory roots.
Hardware evidence
On Nostalgia, J-Link EDU Mini V2 serial
000802011345accessed the attached RP2350 over SWD at a requested 100 kHz. Two fresh sessions per path ran:DPIDR was
0x4c013477, DPIDR1 was0x94, and the discovery root was address zero. Its class 9 ROM walk completed with seven identities, including the two Arm MEM-APs. Both APs returned IDR0x34770008, CPUID0x411fd210, and target-memory debug base0xe00ff000; both memory walks completed with seven identities. The integration limits were depth 8, 64 visits, 256 entry reads, and a ten-second deadline.The example also completed the debug-space walk and both MEM-AP walks using the same provider and serial, with
-debug-space -walk,-ap-base 0x2000 -walk, and-ap-base 0x4000 -walkrespectively. All connection cleanup calls returned successfully. Restored state was not independently measured afterward. No target-memory write, halt, reset, component unlock, or component power request was performed. These walks cover advertised entries; addresses above 32 bits, memory writes, and injected failures have simulation coverage but were not exercised on this bench.