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Add cross-platform packed inference paths - #5

Merged

iamwavecut merged 28 commits into

mainfrom

codex/vulkan-executorch-spike

Jul 12, 2026

Merged

Add cross-platform packed inference paths#5
iamwavecut merged 28 commits into
mainfrom
codex/vulkan-executorch-spike

Commits on Jul 11, 2026
- Add cross-platform packed inference paths
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  33b4653
- Relax realistic AVX2 BF16 test tolerance
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  5ea2e26
Commits on Jul 12, 2026
- ci: compile Vulkan sources on Windows
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- ci: discover the installed MSVC toolchain
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- ci: use Ninja with the discovered MSVC
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- ci: select the installed Visual Studio generator
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- ci: normalize ExecuTorch sources for Windows codegen
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- Fix Vulkan PTE build with CMake 4
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- Document Windows Vulkan build evidence
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- ci: package Windows Vulkan runners
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- ci: record Windows bundle provenance
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- ci: require the official MSVC runtime
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- ci: bundle transitive Windows notices
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- ci: tighten Windows bundle license scope
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- ci: cap the complete Windows bundle
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- Fix CUDA W4A4 and AdaLN paths; speed up Triton activation and matmul
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  30e95a4
- Add SIMD decoders for W2/W3/W6 packed CPU matmul
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- Reuse a persistent CPU worker pool and cache activation-constant validation
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- Document CPU low-bit SIMD coverage and the worker pool in the kernel audit
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  a7667ec
- Tune CPU matmul by CPU family and buffer per-column decode; vectorize early FWHT stages
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- Add a cp.async-pipelined mma64 kernel, enabled by default for W2 only
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- Size MPS threadgroup memory per RPBH block and simplify reductions
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- Fuse the W4A4 GEMM in Triton, cache forward-plan state, and support torch.compile
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- Split the CLI/hub test monoliths, reconcile audit docs, and ship py.typed
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- Refresh the CPU low-bit benchmark table and bump to 0.5.0
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  b8cb1a5
- Gate the mma64 cp.async pipeline by grid occupancy and harden multi-arch builds
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- Tune fused W4A4 tiles by batch size and raise the int_mm crossover
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  3d4208a
- Ship fused W2A4 and direct INT8-activation GEMM paths
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  b8ab9e8

Commits

Commits on Jul 11, 2026

Commits on Jul 12, 2026