Do not hold the CPU for a sprite enabled after the line's DMA compares - #340
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highbyte merged 1 commit intoSep 18, 2026
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The bus stall model counts a sprite that is about to start (enabled, DMA off, Y on the line) among the fetching ones, so that sprite 0's BA window is seen before the compare in cycle 55 has run. That prediction was kept for the whole line: a sprite enabled, or moved onto the line, after both compares got a window although it does not start there, and a read was held for a fetch that never happens. The prediction now ends with the second compare. VICE's spriteenable4 test programs enable sprites 0-2 in cycle 57 of the line their Y names and time the code that follows; they now match on PAL and NTSC.
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What
A sprite enabled (or moved onto the raster line) after the line's two DMA compares, in cycles 55 and 56, does not start fetching on that line. The VIC-II model already had that right, but the bus stall model still gave such a sprite a BA-low window, so a CPU read near the end of the line was held for up to three cycles for a fetch that never happens.
Why it happened
Vic2BusStalls.BuildWindowscounts a sprite that is about to start (enabled, DMA off, Y on the line) among the fetching ones, so that sprite 0's window, which begins in the same cycle as the first compare, is seen before that compare has run. The prediction was used for the whole line. It is now used only until the second compare has been made; from there the VIC-II's DMA state is final for the line.Verification
spriteenable/spriteenable4andspriteenable4_ntsc, which enable sprites 0-2 in cycle 57 of the line their Y names and draw a timing bar with the code that follows. No other result changed; the sprite and DMA suites are 129 of 129.A_sprite_enabled_after_the_compares_takes_no_bus_on_that_line: enabled in cycle 55, a read in cycle 57 waits three cycles; enabled in cycle 57, none.