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Show what a sprite's fetch slot read from the chip's bus, and a halted multicolour pair as the chip does - #339

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highbyte merged 1 commit into
feature/cpu-cycle-enginefrom
feature/c64-vic2-sprite-fetch-line-output
Sep 17, 2026
Merged

highbyte merged 1 commit into
feature/cpu-cycle-enginefrom
feature/c64-vic2-sprite-fetch-line-output

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What

Two details of a sprite drawn on the line its own data fetch happens, each established by one of VICE's test programs.

The bytes a fetch slot reads with the DMA off. A sprite 3-7 with X at or beyond $164 is displayed on the line its compare starts the DMA, with what its fetch slot at the line's start read while the DMA was still off. That was $FF, the idle byte, $FF, with the idle byte read when the line ended. Now:

  • the two bytes of the CPU's half of the slot's cycles are the byte of a VIC-II register access (read or write) the CPU makes in that cycle, $FF when it makes none;
  • the idle byte is the one in place as the line begins.

sb_sprite_fetch/sbsprf24-164 places three bytes of its own this way (STA $D000,Y timed so its dummy read and its write fall in sprite 6's slot, and an idle byte it restores a few cycles later).

A multicolour pair caught by the halt. A sprite still shifting when its own fetch begins repeats its last pixel for seven pixels. When a multicolour pair is taken in the last pixel before the halt, that pixel and its repeats show only the pair's high bit, as a standard pixel would: 01 shows nothing, 11 the sprite colour. spritefetchbug/test-136-2a shows it; the X positions its readme lists are exactly that alignment, so the rule is kept that narrow.

How

  • Vic2: register accesses in a line's first ten cycles (the slots of sprites 3-7) record their byte by cycle, reset per line only when something was recorded; the idle byte is captured at the line's start when an enabled sprite 3-7 with its DMA off has its Y on the line. The run derivation builds the slot's row from those.
  • Vic2SpriteManager.DecodeSpriteRun: a pair taken at the pixel before the halt keeps only its high bit from that pixel on. The run derivation sends such runs through the decoded path, so drawing and collisions both see it.

Verification

  • VICE test programs (274 runs, PAL and NTSC): 250 → 252 match. Newly matching: sb_sprite_fetch/sbsprf24-164, spritefetchbug/test-136-2a. No other result changed.
  • New unit tests: the slot's bytes from a register read and write with the idle byte of that time; the pair rule (11 → sprite colour, 01 → nothing, a pair taken a pixel earlier unchanged).
  • Games (Commando, Giana Sisters; PAL, NTSC, snapshots) and fourteen demos at three frame counts render byte-identically before and after.
  • Performance (MacBook Air M1, For Your Sprites Only): unchanged in every configuration (sequencer with per-line sprites 1288/1305 → 1274/1281 µs/frame).

…d multicolour pair as the chip does

A sprite 3-7 displayed on the line its DMA starts (X at or beyond $164) shows
what its fetch slot at the line's start read while the DMA was off. In place
of the $FF of the two accesses in the CPU's half of the cycle it now carries
the byte of a VIC-II register access the CPU makes in that cycle, and the idle
byte is the one of the line's start rather than the line's end. VICE's
sbsprf24-164 test program places three bytes of its own that way.

A multicolour sprite still shifting when its own fetch halts it repeats its
last pixel; a pair taken in the last pixel before the halt shows only its high
bit there, as a standard pixel would (VICE's spritefetchbug test program).
@sonarqubecloud

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@highbyte
highbyte merged commit 3bf3466 into feature/cpu-cycle-engine Sep 17, 2026
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highbyte deleted the feature/c64-vic2-sprite-fetch-line-output branch September 17, 2026 18:56
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