Model the 6526 timer pipeline and interrupt flag timing, add the CiaSyncedSplit sample

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Summary

The CIA timers get the 6526's pipeline, and the timer-synced test programs and demos fall into place.

• Timer pipeline. A timer counted from its control write's own cycle. On the 6526, after a start the counter holds through the two cycles after the write and shows its first decrement on the third; a force load shows the latch two cycles after the write, holds it one cycle and counts from the fourth; a stop lets the counter move for two more cycles; a one-shot stops with the latch in the counter (was $FFFF); writing the latch's high byte while the timer is stopped loads the counter, the low byte alone does not (was both). CiaTimer keeps its deadline representation (one comparison per catch-up) and adds pending events dated to their cycles.
• Interrupt flag timing. The underflow flag shows in the interrupt control register in the cycle the counter reads 0 for timer A and one cycle earlier for timer B, as on the 6526, and the interrupt output follows a cycle later unless a read took the flag away. VICE's timerbasics/test, 256 interrupt-register reads in a 14-cycle loop against a 15-cycle timer, now matches its hardware dump byte for byte.
• CiaSyncedSplit sample in the Avalonia and browser menus: CIA 2's timer A started in a known cycle, the raster interrupt reads it and delays one count per cycle (the classic stabiliser), and a background split in the opened lower border lands in the same cycle every frame. Two one-pixel sprites mark where its edge belongs; a timer counting from its write puts the edge 24 pixels to their left.
• CIA unit tests rewritten to the pipeline, six new counting cases; docs describe the rules and the harness's CIA suites.

Verification

• VICE harness, 274 VIC-II tests on both models: 220 to 237 match, nothing worse. New: spritesteal PAL and NTSC (the sprite stall accounting was right; the timer offset was not), vsp-tester PAL and NTSC, spritecrunch 3b/3c/3d and 2-07/08/09, spritebug 104/105/106, sb_sprite_fetch-163, colorfetchbug bitmap/main2/main3/main4.
• VICE's CIA test programs (104, exit codes): timerbasics/test and irqdelay's old-CIA variants pass; the cia-timer programs now run to completion and fail only on the 6526's same-cycle read quirks, where before they timed out. We model a 6526 consistently (the 6526A's timing is a follow-up).
• Games A/B against the integration branch: identical for Commando (two snapshots, D64 PAL and NTSC) and Giana Sisters (D64 PAL and NTSC). Demos: 13 identical; For Your Sprites Only moves its timer-synced sprite bars by one cycle, as the timing now dictates.
• The sample's timer value at the interrupt read is exactly the derived one on both models (per-instruction trace), its marks and edge coincide, and on the integration build the edge sits 24 pixels left of the marks.
• Timing (For Your Sprites Only, 600 frames, three repeats, two alternating rounds, MacBook Air M1): no measurable change in any renderer configuration.
• Whole solution builds, both app shells build with the new resource; full test suite passes (the two wall-clock tests pass when run alone).

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Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

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