Latch DEN per cycle in line $30, read the DMA-delay idle byte from $38FF, fix the VICE harness's NTSC names and frame compared

[highbyte]

Summary

Idle-state graphics and DMA-delay follow-ups in the sequencer pixel generator, plus two fixes in the VICE test harness.

• DEN is latched per cycle of raster line $30. The generator read the core's frame latch live while catching up after each instruction, so a DEN bit set partway through line $30 made the cycles before the write bad ones too, and the row counter was always reset at cycle 14. It now keeps its own latch from the journaled $D011: cleared at the line's first cycle, set by any cycle of the line whose DEN is on, including the value at line $31's first cycle (a write lands the cycle after it, so a write in line $30's last cycle still counts and one in line $31's first does not). A DEN set in cycle 13, 14 or 15 of line $30 now gives a normal row, a row whose counter reset was missed (the next row shows in its place) or a row shifted by one column, as VICE's dmadelay test3 references show.
• The DMA-delay idle byte comes from $38FF. The g-access of the cycle in which a mid-line bad line condition arises reads $38FF rather than $3FFF on the 6569 and 6567R8, per the hardware table in VICE's vsp-tester readme (VICE does not model this itself; the test is written against hardware).
• Harness: -ntsc names. The NTSC builds in the dmadelay suite are named with a hyphen; the harness only knew _ntsc and ran them on the PAL machine against NTSC references.
• Harness: the frame compared. The picture is now the frame the exit code was written in, run to its end, which is the frame VICE's exit screenshot shows; it was the frame before, which for a program that exits in its first interrupt frame is the screen its setup was still overwriting.
• Five new sequencer tests; docs updated.

Verification

• VICE harness, 274 tests on both models: 194 to 220 match, nothing worse. 22 dmadelay programs by the suffix, dmadelay test3 at delays $19/$1a on PAL and NTSC by the latch, D011Test/disable-bad on both models and sequencer-bug/bug by the frame compared.
• vsp-tester still exits $FF: it syncs on CIA 1 timer A's boot phase and expects its $d011 write three cycles later than ours lands; a CIA/CPU timing matter, not this branch's.
• Games A/B against the integration branch: identical for Commando (two snapshots, D64 PAL and NTSC) and Giana Sisters (D64 PAL and NTSC).
• Demo A/B: fourteen demos at 1500/4000/8000 frames identical.
• Timing (For Your Sprites Only, 600 frames, three repeats, two alternating rounds, MacBook Air M1): no measurable change in any renderer configuration; sequencer with per-line sprites 1301/1275 vs 1300/1283 us/frame, the rest likewise within the round-to-round noise.
• Whole solution builds; full test suite passes.

[sonarqubecloud]

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

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