mem: add an MI300X-oriented HBM3 x64 interface - #8
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Add a 64-bit HBM3 channel model sized and clocked for the public MI300X memory organization. The interface is intended to be paired by HBMCtrl, giving 128 modeled x64 channels across eight stacks. Use the public AMD MI300X capacity, interface-width, and transfer-rate data. For timings not published by AMD, derive conservative values from the Ramulator 2.1.0 HBM3_16Gb_8hi and HBM3_6400Mbps presets, scaling command timings to the slower MI300X command clock. Document the model assumptions where gem5 cannot directly represent HBM3 hierarchy or fractional command cycles.
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Add a 64-bit HBM3 channel model sized and clocked for the public MI300X memory organization. The interface is intended to be paired by HBMCtrl, giving 128 modeled x64 channels across eight stacks.
Use the public AMD MI300X capacity, interface-width, and transfer-rate data. For timings not published by AMD, derive conservative values from the Ramulator 2.1.0 HBM3_16Gb_8hi and HBM3_6400Mbps presets, scaling command timings to the slower MI300X command clock.
Unlike the generic HBM3 preset in gem5#3271 this interface is parameterized for MI300X’s existing HBMCtrl topology: eight controllers pair sixteen x64 interfaces per stack. Its capacity and burst timing reproduce 24 GB and approximately 665 GB/s per stack, or 192 GB and 5.3 TB/s across the package.