NCC-Sign hardware/software co-design

FPGA accelerator and embedded-software integration for the post-quantum signature scheme NCC-Sign on a Xilinx Zynq platform.

The design accelerates the polynomial and hashing operations that dominate lattice-based cryptography while retaining signature-scheme control in software.

Architecture

• Parameterizable NTT/INTT datapath
• Point-wise polynomial multiplication
• Keccak/SHA-3 hardware module
• Memory-mapped software interface for accelerator control and data transfer
• Separate trinomial-cyclic and non-cyclic NCC-Sign software configurations
• On-board cycle measurements for key generation, signing, and verification

Target platform

• Xilinx ZedBoard / Zynq-7000
• Vivado 2020.2
• Vitis 2020.2
• Serial terminal for benchmark output

Repository layout

• rtl_verilog/ — synthesizable accelerator RTL and Xilinx IP configuration files
• sim_verilog/ — module-level Verilog testbenches
• SWCODE_TC/ — trinomial-cyclic NCC-Sign software and hardware-access layer
• SWCODE_NC/ — non-cyclic NCC-Sign software and hardware-access layer
• HW_vivado_made/ — packaged IP metadata, exported hardware platform, bitstream, boot image, and board notes

Reproducing the board workflow

1. Add the packaged accelerator IP (HW_vivado_made/component.xml) to a Vivado 2020.2 project.
2. Integrate the accelerator with the Zynq processing system and export the hardware platform.
3. Build either SWCODE_TC or SWCODE_NC as a Vitis application against the matching hardware design.
4. Program the board or create a QSPI boot image.
5. Capture the UART output to compare key-generation, signing, and verification cycle counts.

Prebuilt ZedBoard artifacts are included for reproducibility. See HW_vivado_made/flash_README.md for the QSPI boot procedure.

Scope

The repository is an FPGA research prototype tied to a specific tool and board flow; it is not a portable software package. The cryptographic implementation and generated hardware artifacts should be independently reviewed before any production use.