Unable to load into Innovus, LEF/DEF errors.

[bunchgrape]

Hi,

I'm trying to load the designs using the given LEF&DEF raw data from Google Drive.
I found the lef/def/verilog files have some problems and mismatches.

E.g., I'm loading "1-RISCY-a-1-c2-u0.7-m1-p1-f0.def" and "circuitnet.lef", some of the LEF vias are not defined. Some instances used in the DEF file cannot be found in the LEF.

Can you help with it? Thanks.
The command I used for loading is

loadLefFile ../dataset/CircuitNet-N28/raw_data/circuitnet.lef
loadDefFile ../dataset/CircuitNet-N28/raw_data/def/DEF/1-RISCY-a-1-c2-u0.7-m1-p1-f0.def

[funny-Mr-zhi]

Hi there, I've run into the exact same issue as described here. For reference, here are the details of the failure I'm observing:

[failure] 5866-RISCY-FPU-b-1-c2-u0.7-m2-p8-f1 | cause: lake LEF Macro size definition (total 10 kinds): ['apb_event_unit_1', 'apb_spi_master_1', 'apb_pulpino_1', 'axi_spi_slave_wrap_1', 'periph_bus_wrap_1', 'apb_fll_if_1', 'apb_timer_1', 'adv_dbg_if_1', 'apb_uart_1', 'apb_i2c_1']