Value circuits new#36
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RIP Fable.. I find that I typically mix and match accum :: Circuit (Signal dom Int) (Signal dom Int)
accum = circuit \(Fwd (Values i)) -> do
Fwd (Values acc) <- registerC 0 -< Fwd (Values acc')
let acc' = acc + i
idC -< Fwd (Values acc')~ accum :: Circuit (Signal dom Int) (Signal dom Int)
accum = circuit \(Fwd (Values i)) -> do
let
Values acc = register 0 (Values acc')
acc' = acc + i
idC -< Fwd (Values acc')Not sure about any of this, just floating an idea. |
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I'll think about it but adding support in general Haskell expressions and bindings might open a whole can of worms. Right now, since it's limited to the "arrow land", it's relatively simple without much in the way of edge cases (I hope). I'm generally in favour of keeping the plugin simple and predictable at the cost of a bit of verbosity. You can always use helpers (something like |
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Yeah, makes sense. I'd rather have less magic too. |
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Since #14 the error locations often pointed to the end of the circuit instead of the correct location. Locate each generated binding at its circuit expression so GHC blames the offending statement. The regression test is in a separate PR. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Compiles tests/fixtures/BusError.hs (a deliberate type error on a bus) with the plugin enabled and asserts that GHC reports the error on the offending line rather than at the end of the circuit block. Under cabal the plugin is found via the package environment file. Under `nix build` the package isn't registered in a package db during its own check phase, so the flake points GHC_PACKAGE_PATH (via the builder's NIX_GHC_PACKAGE_PATH_FOR_TEST hook) at the in-place db, letting the test run for real there too. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Value-group logic is lifted to the signal level with `fmap` over a
`bundle` of the group's inputs. Two strictness points there can make
combinational feedback between value groups deadlock simulation:
* `bundle` lifts its first element with `fmap` / `mapSignal#`, which
forces that element's spine. Prepend a lazy unit so no real input
sits in that spine-forcing head slot.
* The logic function matched its inputs strictly, so a constructor
pattern at the boundary (destructuring the sampled value) forced its
input to produce *any* of the group's outputs -- even outputs that do
not use it. That deadlocks when the input depends, through the
circuit, on such an output. Match each value input lazily
(irrefutable), as the bus-level plumbing already does, so an output
only forces the inputs it actually uses.
Both keep value-group feedback well founded without changing the lifted
logic. The library and error-location test suites still pass.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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| A block can span several clock domains: the value-level bindings are | ||
| split into groups connected by shared variables and each group is lifted | ||
| with its own `fmap`/`bundle`/`unbundle`, so only buses whose values | ||
| actually meet must share a domain. Sharing a value across domains is | ||
| rejected by the type checker. Lets that don't touch value land stay at | ||
| the bus level, so let-bound sub-circuits can be used with `-<`. | ||
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| The value markers have distinct semantics: `SignalV x` asserts the | ||
| bus is a `Signal` (best inference — it works against fully generic | ||
| sub-circuits); `FwdV x` samples/drives the forward channel of any | ||
| signal-like bus via the new `SignalBus` class (`Signal`s, `Vec`s and | ||
| tuples of them, custom buses) but needs the bus type determined by | ||
| context; and `DSignalV x` is `SignalV` for delayed signals — the delay | ||
| index is part of the bus type, so a logic group's values must all sit at | ||
| the same pipeline depth, and its outputs are produced at that depth. | ||
| Mixing plain and delayed markers in one group is reported by the plugin. | ||
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| The value boundary is generated with the new `SigTag`, `FwdTag` and | ||
| `DSigTag` pattern synonyms (`Circuit` module); `SigTag`/`DSigTag` pin the | ||
| bus type so that type inference survives nested circuits (the `Fwd` | ||
| family is not injective) and "too shallow" `SignalV` markers report a | ||
| direct `Vec`-vs-`Signal` style mismatch. **Breaking**: `ExternalNames` | ||
| gained `signalTagName`, `fwdTagName` and `dSignalTagName` fields, so | ||
| custom plugins (e.g. clash-protocols style) need to supply them — | ||
| `defExternalNames` is now exported so they can be record updates of the | ||
| defaults. |
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For the changelog specifically, I feel only the first paragraph is necessary. All other info should be in documentation / README.
| instance (SignalBus a, SignalBus b, BusDom a ~ BusDom b) => SignalBus (a, b) where | ||
| type BusDom (a, b) = BusDom a |
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I guess this should be generated using TH. Up to a 3-tuple seems a bit meager.
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It's now up to 12 for everything.
| -- unifies the domains via the generated bundle before it checks the slave | ||
| -- pattern), so the marker sits on the @circuit@ line. |
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You mean, this always happens? I would expect it to happen either at the introduction of a or b.
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Yeah, ideally it should. I'll see if I can get it to error there.
Keep the summary and the breaking ExternalNames change; the marker semantics and multi-domain details live in the README and haddocks. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
SignalBus previously stopped at 3-tuples. Extend it (and the Fwd/Bwd, TrivialBwd and BusTagBundle instances it leans on) to 12-tuples, and exercise a tuple bus with an FwdV marker in the examples and tests. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Generated tuple patterns and expressions had no source location, so a type error on a whole bundle -- e.g. a cross-domain mismatch discovered while checking the slave pattern of a value circuit -- fell back to the head of the circuit expression. Give them the combined span of the ports they bundle, so the error points at the pattern that introduces the offending ports. The CrossDomainError fixture now puts its markers on a different line than the circuit keyword to pin this down. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
The value level circuit syntax I originally started work on 6 years ago! master...value-circuits
This was written with the anthropic's new fable model. I also got it to add significantly more testing.
This gets you pretty close to being able to write everything with circuit syntax! Mealy machines can be done with a
registerC:It also supports multiple clock domains (although you don't get a great error when you mix them up):
and
DSignalCsupport (makes sure all groups have the same delay):I've tested this enough internally that I'm happy with it. The only issue that came up is the lazyness which has been fixed.