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Add RISC-V Vector Extension implementation of from_chars - #196

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pdimov merged 10 commits into
boostorg:developfrom
e4d08:feature/from_chars_rvv
Sep 14, 2026
Merged

pdimov merged 10 commits into
boostorg:developfrom
e4d08:feature/from_chars_rvv

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@e4d08

@e4d08 e4d08 commented Jul 23, 2026

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This adds a RISC-V Vector (RVV) implementation of the from_chars algorithm, ported from the x86 SIMD implementation. The implementation supports VLEN >= 128 and handles narrow and wide character types (char, char16_t, char32_t).
This PR is heavily inspired by Andrey Semashev's work on x86 SIMD implementations.

The performance effect on Spacemit-X60 (riscv64), gcc 16.1.0, in millions of successful from_chars() calls per second:

Char     | Generic | RVV
=========+=========+================
char     |  4.123  | 11.249 (2.73x)
char16_t |  4.117  |  9.128 (2.22x)
char32_t |  4.301  |  7.754 (1.80x)

The unsuccessful parsing case depends on where the error happens, as the generic version may terminate sooner if the error is detected at the beginning of the input string, while the SIMD version performs roughly the same amount of work but faster. Here are some examples for 8-bit character types (for larger types the numbers are more or less comparable):

Error              | Generic  | RVV
===================+==========+================
EOI at 35 chars    |   3.782  | 10.109 (2.67x)
EOI at 1 char      | 145.204  | 10.998 (0.08x)
Missing dash at 23 |   6.625  | 11.329 (1.71x)
Missing dash at 8  |  17.294  | 11.575 (0.67x)
Illegal char at 35 |   4.354  | 10.720 (2.46x)
Illegal char at 0  | 106.487  | 11.016 (0.10x)

Early errors (EOI at 1 char, illegal char at 0) are significantly slower with RVV — the 1-character input cannot amortize the SIMD setup cost, resulting in a ~13x slowdown. This is consistent with the x86 implementation's behavior, which shows the same pattern.
The missing dash at position 8 case shows a slight regression (0.67x), unlike x86 which achieves a speedup for this scenario. This is likely because the RVV implementation uses two separate expected dash vectors — one per deinterleaved character pair — rather than x86's single shuffled vector. The early error at position 8 does not recoup the overhead of this approach.
Late errors and successful parses all show worthwhile speedups ranging from 1.71x to 2.73x. In general, for inputs where the SIMD path can reach its full processing width, the RVV implementation provides a consistent ~2x improvement over the generic path across all character types.
The test code that was used for benchmarking is the same as the one in PR #186 (with running the successful parse twice for warmup):
uuid_from_chars_perftest.cpp

Compile and run with:

g++ -O3 -march=rv64gc -std=gnu++17 -I. -o uuid_from_chars_perftest_generic uuid_from_chars_perftest.cpp
g++ -O3 -march=rv64gcv -std=gnu++17 -I. -o uuid_from_chars_perftest_rvv uuid_from_chars_perftest.cpp

taskset --cpu-list 1 ./uuid_from_chars_perftest_generic 
taskset --cpu-list 1 ./uuid_from_chars_perftest_rvv

e4d08 added 2 commits July 23, 2026 14:32
The BOOST_UUID_USE_RISCV_V config macro is automatically defined when
the compiler defines __riscv_v, indicating RISC-V Vector Extension
(V 1.0+) support is available. The macro is also added to the
BOOST_UUID_NO_SIMD exclusion list.
This adds a RISC-V Vector (RVV) implementation of the from_chars
algorithm, ported from the x86 SIMD implementation. The RVV version
supports VLEN >= 128 and handles narrow and wide character types
(char, char16_t, char32_t).

The implementation follows the same structure as from_chars_x86.hpp:
deinterleaving of input character pairs, dash validation, hex character
validation, and nibble packing. It uses two separate expected dash
vectors (one per character pair) instead of x86's single shuffled
vector, as RVV's vrgather-based deinterleaving makes this approach
more natural.

The generic fallback path is preserved: both the x86 and RISC-V SIMD
paths dispatch to from_chars_generic when std::is_constant_evaluated()
is true.
@pdimov

pdimov commented Jul 24, 2026

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That's interesting but we need a way to test it.

@e4d08

e4d08 commented Jul 24, 2026

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I could add RISC-V tests to the CI, but I need your opinion on the best way of doing it. I consider cross-compiling and running tests under QEMU, but maybe there are better options. If cross-compiling is eligible, let me know and I will implement it.

@pdimov

pdimov commented Jul 24, 2026

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I don't know of a better way, so we could try that. But please use a separate PR for it.

@e4d08

e4d08 commented Sep 10, 2026

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@pdimov Hello! Testing is ready at #197. Is there anything else needed?

Comment thread include/boost/uuid/detail/from_chars_riscv.hpp Outdated
Comment thread include/boost/uuid/detail/from_chars_riscv.hpp Outdated
Comment thread include/boost/uuid/detail/from_chars_riscv.hpp Outdated
Comment thread include/boost/uuid/detail/from_chars_riscv.hpp Outdated
Comment thread include/boost/uuid/detail/from_chars_riscv.hpp Outdated
Comment thread include/boost/uuid/detail/from_chars_riscv.hpp Outdated
Comment thread include/boost/uuid/detail/from_chars_riscv.hpp Outdated
Comment thread include/boost/uuid/detail/from_chars_riscv.hpp Outdated
Use the number of available characters as the vector length instead of
copying them into a zero-initialized temporary buffer. The lanes above n
are tail-agnostic, but they are never observed, since the parse has
already failed and the result is not stored. With the temporary buffers
gone, the memcpy helper is no longer used and its include is dropped.
Template the core on the character type and load each constant where it
is used instead of passing seven preloaded vectors, shortening the
signature. No change in behavior.
Check __riscv_vector and __riscv_v_min_vlen instead of __riscv_v, so that
targets with shorter vectors (Zve32*, Zve64*) use the generic
implementation rather than producing incorrect results. The vector length
the algorithm requires is now specified where it is used instead of being
passed around as a vl parameter.
The valid masks were only negated right after being computed, so a single
non-zero test replaces the vmseq/vmnand pair.
All four dashes are at character positions 8..23, so sliding chars1 down by
8 and chars2 into lanes 8..15 gives a single vector to check against one
dash constant, instead of two comparisons plus a dash character splat. The
middle constant replaces mm_expected_dashes1 and mm_expected_dashes2.
load_vector128 was a one-line wrapper around the load intrinsic. Inline it
at its call sites, where the required vector length is already available as
the local vl.
@e4d08
e4d08 force-pushed the feature/from_chars_rvv branch from b730de9 to 2dafb46 Compare September 12, 2026 21:54
@Lastique

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Looks good to me.

@pdimov
pdimov merged commit 16a0681 into boostorg:develop Sep 14, 2026
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3 participants