This project implements a multicycle RISC-V processor core using SystemVerilog. The design focuses on efficient hardware utilization by breaking instruction execution into multiple clock cycles and sharing functional units like the ALU and Memory.
- Architecture: Multicycle (Non-pipelined)
- Supported Instructions: R-type (add, sub, and, or, slt), I-type (addi, lw), S-type (sw), and B-type (beq).
- Technology: SystemVerilog, simulated using Questa/ModelSim.
- Verification: Waveform-based verification for each execution state.
top.sv: The top-level module connecting the controller and datapath.controller.sv: FSM-based control unit managing execution states (Fetch, Decode, Execute, etc.).alu.sv: Arithmetic Logic Unit for core operations.datapath.sv: Internal routing, registers, and multiplexer logic.
Below is the full execution waveform proving the correct processing of the instruction set.
The step controller ensures that each micro-operation is completed within its designated clock cycle. The state transitions are monitored to verify the accuracy of the multi-cycle flow.
