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SYN-40 - A JLCPCB tier that can drill the holes a module footprint ships - #254
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Byte-for-byte from `origin/SYN-jlc-advanced-drill`. Every KiCad ESP32-WROOM-32 footprint drills twelve 0.2 mm thermal vias into the ground paddle, and no profile could make them: jlc-standard, pcbway-standard and jlc-filled-via floor at 0.3 mm, oshpark-4layer at 0.25 mm. The board below carries that module, so without this it declares a process it cannot be built on. Identical to absmach#254, so whichever lands first the other is a no-op.
SammyOina
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[P1] Enforce the profile's supported layer count
The capability descriptor advertises jlc-advanced for [4, 6] layers, but the runtime profile resolution uses only the manufacturer string. ManufacturerProfile has no layer applicability, so a 2-layer board can select jlc-advanced, pass the 0.2 mm/via-in-pad checks, and be treated as fabrication-ready even though it does not match the declared process.
Please validate the selected profile against board.layers before routing/DRC and add a regression test showing that jlc-advanced is rejected on a 2-layer board. The descriptor alone is not sufficient to enforce this constraint.
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Fixed in a7a2994. |
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[P1] Enforce layer applicability in all fabrication/DRC consumers
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Fixed in 20a11cb. |
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[P1] Constrain The new layer-aware resolver does not constrain |
…tprint ships Every KiCad ESP32-WROOM-32 variant — plain, D, E, U and UE — drills twelve 0.2 mm thermal vias into the ground paddle. No profile could make them. `jlc-standard`, `pcbway-standard` and `jlc-filled-via` floor at 0.3 mm and `oshpark-4layer` at 0.25 mm, so a board carrying that module declared a process it was knowingly violating, which is a qualification failure rather than a rounding error. `jlc-advanced` is the tier JLCPCB sells for exactly this: the 0.2 mm minimum via hole on four- and six-layer builds. It is built on `jlc-filled-via` rather than on the plain tier because those holes sit inside pad 39, so they need the fill as well as the drill. Only the drill moves. Trace width, clearance, edge clearance and the annular ring stay on the standard floor, for the reason `jlc-filled-via` already records: a board that names a tier to reach one capability is not also handed geometry it never paid for. The ring in particular did not have to move — the paddle's vias sit on 0.6 mm pads, a 0.2 mm ring, which already clears the 0.13 mm floor. The drill was the only thing in the way. Matched exactly, like `jlc-filled-via`, so `jlcpcb` and `JLCPCB advanced` both still resolve to the conservative floor. A board gets the tier it named or `jlc-standard`, never a surcharged process by accident; there is a test for each of those spellings. Also listed in the capability descriptor, under `fab_profiles` and `profiles_offering_via_in_pad`, so `synth capability` does not advertise a smaller set of processes than the code offers.
The capability descriptor advertised `jlc-advanced` for 4 and 6 layers, and nothing enforced it. `ManufacturerProfile` carried no layer applicability and resolution matched on the manufacturer string alone, so a 2-layer board could declare the tier, clear the 0.2 mm drill and via-in-pad checks against a floor no fabricator had agreed to, and be reported fabrication-ready. `supported_layers` puts the restriction on the profile itself, and `E-SYNTH-PROCESS-004` enforces it at ERC, before routing or DRC. Empty means offered on every stackup, which is what the three stock tiers are and what every profile TOML written before this field meant: their floors are the fabricator's baseline and do not depend on how many layers are stacked. Six tests. The profile knows which counts it is sold for and the stock tiers stay unconstrained; the rule refuses `jlc-advanced` on 2 layers naming the stackup in the finding, accepts it on 4 and 6, leaves every stock tier alone on 2, 4 and 6, and says nothing about an undeclared manufacturer — that is `E-SYNTH-PROCESS-002`'s job, which already resolves an unstated tier the same way the router and the DRC do.
`E-SYNTH-PROCESS-004` reports the mismatch, but it only fires through the validator. Every other consumer resolves the profile for itself and took the floors `from_name` returned: the exporter's `.kicad_dru`, the ampacity width in `pcb.rs`, `synth route`, `synth export-kicad` and the MCP signal-integrity tool. A 2-layer board declaring `jlc-advanced` was therefore judged against a 0.2 mm drill and via-in-pad on the direct DRC path and could be reported fabrication-ready against a process no fabricator sells. So the refusal belongs in resolution, not in a rule those paths do not run. `for_layers` resolves the name and then checks the stackup, falling back to `jlc-standard` when the pairing is not offered -- the same conservative answer an unrecognised name gets, for the same reason. The fallback is visible rather than silent: `DrcReport` carries the profile's name, and it reads `jlc-standard` where the board said otherwise. All six fabrication and DRC consumers now go through it. `from_name` stays for the question it actually answers, which is what a name means. Two tests: the advanced tier resolves to the conservative floor on 2 layers and keeps its 0.2 mm drill and fill on 4 and 6; and every stock tier, including an unrecognised name, resolves identically on 2, 4 and 6, so boards that were building before the restriction existed are not downgraded.
…nst the layer count The previous commit sent every fabrication consumer through `for_layers`, but two still resolved the profile by name alone: - `RouteRequest::use_profile_floor`, which sets the router's drill, clearance and ring floors and the via-in-pad capability for the CLI and all three MCP routing paths. A 2-layer board naming `jlc-advanced` was routed, escaped and gated against a 0.2 mm drill and a fill the tier is not sold with at that count, and `requires via_in_pad` was granted. - the board setup `pcb.rs` writes into the exported `.kicad_pcb`, added on main after this branch was cut. `use_profile_floor` now takes the layer count and resolves through `for_layers`, and each caller passes `board.layers`. A router test pins the 2-layer and 4-layer answers for `jlc-advanced`.
absmach#164 (component `escape` blocks) already claims E-SYNTH-PROCESS-004 for an unknown escape method and 005 for an escape layer the board does not have, with diagnostic pages and fixtures for both. This branch used 004 for an unrelated rule, so whichever merged second would give one code two meanings and two pages at the same path. The tier-not-offered-for-this-stackup rule moves to 006: the code, its diagnostic page, the doc comments that cite it and the test.
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Review — changes requestedCI passes and the earlier One blocking issue remains: [P1] Please set I would not approve until this mismatch is fixed. |
Follow-up required — add the filled-via layer regression testThe latest commit correctly sets The remaining gap is test coverage: please add a regression test proving that Once this coverage is added and passes, the PR should be ready for approval. |
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Added regression test: jlc-filled-via is offered on 2/4 layers only and resolves to the conservative floor on 6 layers. Descriptor already lists [2,4]. |
What type of PR is this?
This is a feature
What does this do?
Adds
jlc-advanced:jlc-filled-viawith a 0.2 mm minimum drill. Nothing else moves off the standard floor.Which issue(s) does this PR fix/relate to?
Answers the declared-process finding on #184. No profile could drill the ESP32 paddle vias.
Have you included tests for your changes?
Yes, three: only the drill moves, the paddle geometry fits, and
jlcpcbstill resolves tojlc-standard.Did you document any new/modified features?
Yes, on
jlc_advancedand in the capability descriptor'sfab_profilesandprofiles_offering_via_in_pad.Notes
All five KiCad ESP32-WROOM-32 footprints drill twelve 0.2 mm paddle vias on 0.6 mm pads.