Bug: a ground pour split by tracks leaves an island with no via, and nothing ties it back #279

What were you trying to achieve?

Route the standalone Class-A I2C sensor node — two layers, ground poured, 23
nets — and get a fabricable package.

What are the expected results?

The ground pour is one electrical net. Whatever tracks cut it into separate
regions, every region is tied back to the rest, which on a two-layer board
means a via to the other layer's pour.

What are the received results?

The pour comes out in two pieces and one of them is connected to nothing:

validation_failed: kicad-routing-tools (23 connected net(s), 0 open, 349 segment(s), 78 via(s))
  blocking: kicad-cli pcb drc reported 1 blocking violation(s)
  kicad-cli pcb drc: 0 error(s), 1 unconnected, 1 warning(s)

and the unconnected item is the pour against itself:

error unconnected_items  Missing connection between items
      Zone [GND] on F.Cu, priority 1
      Zone [GND] on F.Cu, priority 1

Everything else is clean: all 23 nets close, nothing is open, no via lands in
a pad, no track is under the trace floor, and the only violation at any
severity is one 0.1 mm dangling track stub. The split pour is the whole
difference between this board and a fabricable one.

The same finding appeared on protected_power_entry at an earlier placement
and then went away when the placement changed, which is the behaviour of a
geometry coincidence rather than a property of either board.

Steps To Reproduce

1. synth export-kicad qualification/class-a/i2c-sensor-node/i2c_sensor_node.synth --out <dir> --router kicad-routing-tools
2. kicad-cli pcb drc reports one unconnected item, and it names Zone [GND]
   twice.

In what environment did you encounter the issue?

KiCad 10.0.6, KiCadRoutingTools caad45c, synth from main at dddda6f,
jlcpcb, two layers, 37 components with a 20-pin through-hole header.

Additional information you deem important

Two layers with a through-hole header is the shape that provokes it: the
header's twenty drilled pads punch through both pours along one edge, and
tracks leaving the MCU cut the remainder, so an F.Cu region ends up with no via
to B.Cu anywhere inside it.

What is missing is a pass that reads the poured polygons — which independent
validation already does, since it records plane_splits from
filled_polygon — and ties any island with no via of its own back to the
other layer. The information is there; nothing acts on it.

Until then a split pour is invisible until kicad-cli pcb drc runs, and a
board that is otherwise complete is refused for a reason no diagnostic names:
the routing report says 23 of 23 nets connected and zero open, because the
islands are the same net and the net is connected — just not all of its
copper.

Related but different: #183 is a stitching via landing on another net's pad,
#165 is a plane pad that cannot be stitched at all, #234 is plane fanout
reading synthesized pad geometry. This one is an island of correct pour with no
via in it.

Found while making the Class-A boards standalone: #268.