Bug: the board outline is set by which canvas the placer happened to succeed on, not by the circuit #233

What were you trying to achieve?

Add the furniture a real memory module carries to the Class-C SDRAM card
(#191) — presence detect, thermal provision, supply filtering and series
damping on the shared bus — and have the board stay the size the circuit
needs.

What are the expected results?

Adding 111 mm² of courtyard to a 1335 mm² board grows it by about 111 mm².

What are the received results?

It doubled. Same board, same connectors, 35 more parts:

The outline is not fitted to the circuit — it is fitted to whichever rung of a
four-entry ladder the placement happened to succeed on. Instrumenting
place_with_tuning_impl:

SYNTHDBG courtyard=2240.7 needed=4979.3 compact_side=85.56 extra_margin=1.5
SYNTHDBG placed on candidate 120.00 x 100.00, compact=true
SYNTHDBG compaction moved nothing; outline left at 108.59 x 85.84

The ladder is [(compact_side, compact_side), (100, 80), (120, 100), (160, 120)] (crates/synth-place/src/lib.rs:1196). The first two rungs
failed, the third — 12000 mm² for a 1446 mm² circuit — succeeded, and the
outline was then fitted around parts that had spread across it.

Why a too-large canvas is not just empty border. Every part carrying a
hard edge hint is placed against the canvas edge, so the two 2 × 20
headers on this card sit on the left and right edges of whatever canvas was
chosen: at 120 mm wide they end up 108.59 mm apart, and the fitted outline
keeps that. The canvas size becomes the board size for any design with
edge-mounted connectors.

The same board with the damping resistors' hints softened from hard to
soft succeeds on an earlier rung and comes out 88.59 × 73.94 mm, 22.1%
fill — a 30% area difference from a hint that should not change the board's
size at all.

Steps To Reproduce

1. synth place qualification/class-c/sdram-memory/sdram_memory.synth on the
   board from SYN-40 - Class C case 2: a x32 SDRAM card with declared bus skew budgets #191.
2. Read board_outline, then divide the summed F.CrtYd areas by its area.
3. Add parts and repeat: the outline moves in jumps, not in proportion.

In what environment did you encounter the issue?

synth main at 2a8a6b4, KiCad 10.0.6 libraries, placement only — no router
involved.

Additional information you deem important

A fix that does not need a better packer: once a placement has succeeded, the
envelope the parts actually occupied is known, so re-placing on a canvas cut
to that envelope converges on the size the circuit needs, at one placement run
per step. The ladder then only has to find a feasible canvas rather than a
well-chosen one.

Two other figures worth having in view while reading the constant
FILL_RATIO = 0.45: it is applied to courtyards inflated by
extra_margin_mm (1.5 mm on every side of every part, which more than
triples an 0402), and compact_side adds a flat 15 mm — 60% extra area on a
65 mm board, 6% on a 215 mm one.

#231 is the other half of the same symptom, measured on the same board, and
independent of this.