Issues

• Gemma4 prefill FFN: gate|up as one GEMM with interleaved weight columns (needs a layout change across prefill and decode)

  Xilinx/mlir-air#2067 · Filter by author erwei-xilinx opened on Oct 6, 2026

• air-fuse-alloc-dealloc asserts (NULL operand in fold) on a per-core buffer used by a herd with RTP-bounded loops

  Xilinx/mlir-air#2041 · Filter by author erwei-xilinx opened on Oct 1, 2026

• Core DMA BD chain follows static channel.get order; gets under RTP-bounded loops silently misroute data

  Xilinx/mlir-air#2040 · Filter by author erwei-xilinx opened on Oct 1, 2026

• [fused_decode_ple] no-PLE build returns non-deterministic output across dispatches

  Xilinx/mlir-air#2009 · Filter by author erwei-xilinx opened on Sep 21, 2026

• [gemma4_e2b_q4nx] Prefill initialization exceeds the hardware-context limit

  Xilinx/mlir-air#2005 · Filter by author tonyjie opened on Sep 20, 2026

• [AIRToAIE] Revisit memtile packet S2MM channel-separation: root cause of collapsed-flow deadlock

  Xilinx/mlir-air#1713 · Filter by author erwei-xilinx opened on Jul 8, 2026

• Replace opt-in DMA-scheduling attributes with compiler analyses (from #1705)

  Xilinx/mlir-air#1706 · Filter by author erwei-xilinx opened on Jul 8, 2026

• scf.for iter_args carrying vector<32xbf16> not accumulating across iterations in air.herd body

  Xilinx/mlir-air#1591 · Filter by author erwei-xilinx opened on May 7, 2026
  1

• Extend lightweight herd cloning to tiled unroll path in air-opt-shim-dma-bds

  Xilinx/mlir-air#1558 · Filter by author erwei-xilinx opened on Apr 27, 2026

• use_lock_race_condition_fix should be enabled by default for multi-tile MemTile designs

  Xilinx/mlir-air#1478 · Filter by author erwei-xilinx opened on Mar 28, 2026

• New op: air.rank — multi-device / multi-host parallelism above air.launch

  enhancement
  Xilinx/mlir-air#1414 · Filter by author SamuelBayliss opened on Mar 12, 2026
  3

• Is it possible to automatically generate the source code in the GEMMCaseStudy document?

  Xilinx/mlir-air#857 · Filter by author micropuma opened on Jan 16, 2025
  1

• Documenting air coding practices

  documentation
  Xilinx/mlir-air#770 · Filter by author erwei-xilinx opened on Nov 11, 2024
  1

  

• Required Arguments to Herd Function

  question
  Xilinx/mlir-air#669 · Filter by author hunhoffe opened on Jul 16, 2024
  12

• Python Multiple Segment Examples

  Xilinx/mlir-air#665 · Filter by author hunhoffe opened on Jul 12, 2024

• Channel Operations May Fail Depending on DeallocOp() Placement

  Xilinx/mlir-air#660 · Filter by author hunhoffe opened on Jul 10, 2024
  2

• Worker-to-Self Channel Example

  Xilinx/mlir-air#654 · Filter by author hunhoffe opened on Jul 8, 2024
  5

• Channel Examples

  enhancement
  Xilinx/mlir-air#648 · Filter by author hunhoffe opened on Jul 3, 2024
  

• Multiple launches, herd with single core

  question
  Xilinx/mlir-air#627 · Filter by author hunhoffe opened on Jun 27, 2024
  9

• Build instructions/getting started for RyzenAI / XRT

  Xilinx/mlir-air#494 · Filter by author fifield opened on Mar 13, 2024
  6

• Build instructions clarification in docs

  Xilinx/mlir-air#492 · Filter by author newling opened on Mar 12, 2024

• Form Herds from Multiple scf.forall nests.

  Xilinx/mlir-air#489 · Filter by author SamuelBayliss opened on Mar 11, 2024
  2

  

• Undefined symbol on test 21

  Xilinx/mlir-air#457 · Filter by author gabrielrodcanal opened on Feb 26, 2024
  1

• Herd parameters allow general behaviour, but current lowering does not support this.

  Xilinx/mlir-air#429 · Filter by author SamuelBayliss opened on Feb 16, 2024

• Launch MLIR code on VCK5000?

  Xilinx/mlir-air#387 · Filter by author medbzkst opened on Jan 15, 2024
  4