coralnpu: bump upstream to f57ff99 (Zfbfmin + speculative fetch + reorder buffer)#192
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mguthaus wants to merge 1 commit into
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coralnpu: bump upstream to f57ff99 (Zfbfmin + speculative fetch + reorder buffer)#192mguthaus wants to merge 1 commit into
mguthaus wants to merge 1 commit into
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…order buffer) Range 7731fd6e..f57ff99c (131 upstream commits across ~115 days). Major coralnpu architectural additions: - Zfbfmin extension (BF16 minimal — convert + classify) — f57ff99 - Pipelined speculative fetching + fetch reorder buffer (542945e, 265b3a4, 4706d34, 051b224, f342ed6, 135085b, d8b8f84) - Fetch ibus access upgraded to IrrevocableIO (2b3e3d2) - RVV: corrected lane operand role matching in VFSGNJ exec (c162a82), gate RVVInstructions (3341130), RVV integer/float matmul perf opts - VSI: rvvi monitor/agent updates, UVM batch-mode assertion recovery - Netlist Targets Migration (3105930) Regen: chisel -> sv2v -> perl strip pipeline via dev/setup.sh. CoreMiniAxi.v diff: +5846 / -3038 lines (8884 total), top module still named CoreMiniAxi. Workaround during regen: GitHub codeload returned 502 Bad Gateway on the mpact-riscv tarball direct-archive URL but worked via the codeload/.../tar.gz/<sha> URL. Tarball pre-populated into the bazel content-addressable cache (sha256=b88d3825...) so the inner http_archive fetch hit local cache instead of re-trying the 502. Once the GitHub edge cache stabilizes, the workaround dissolves — no source changes were needed in the coralnpu repo itself. Also gitignore designs/src/coralnpu/dev/packages/ (local install of bazel-7.4.1 / py-3.10.9 / srecord / sv2v required by setup.sh). Build verification deferred to upstream cache sweep. coralnpu is cached on asap7 + nangate45 pre-bump, so the cache run will surface any regression from the fetch-reorder-buffer rework or Zfbfmin extension. Closes #81.
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Summary
Bump
designs/src/coralnpu/dev/repo7731fd6e→f57ff99c(131 upstream commits / ~115 days). Major coralnpu architectural additions in this range:f57ff99542945e,265b3a4,4706d34,051b224,f342ed6,135085b,d8b8f842b3e3d2c162a82), gate RVVInstructions (3341130), integer/float matmul perf optimizations3105930)Regen: chisel → sv2v → perl strip pipeline via
dev/setup.sh.CoreMiniAxi.vdiff: +5846 / −3038 lines (8884 total). Top module stillCoreMiniAxi.Workaround during regen
GitHub codeload returned 502 Bad Gateway on the
mpact-riscvtarball direct-archive URL but worked via thecodeload/.../tar.gz/<sha>URL. Pre-populated the tarball into Bazel's content-addressable cache (sha256=b88d3825...) so the innerhttp_archivefetch hit local cache instead of retrying the 502. Once the GitHub edge stabilizes, the workaround dissolves — no source changes were needed in the coralnpu submodule.Also gitignore
designs/src/coralnpu/dev/packages/(local install of bazel-7.4.1 / py-3.10.9 / srecord / sv2v required by setup.sh).Test plan
dev/setup.shruns clean (after tarball-cache workaround for 502); chisel-emit-verilog target completes, sv2v + perl strip pipeline finish.bazel build //designs/{asap7,nangate45}/coralnpu:coralnpu_gallery— deferred to upstream cache sweep. coralnpu is cached on asap7 + nangate45 pre-bump, so the cache run will surface any regression from the fetch-reorder-buffer rework or Zfbfmin extension.Closes #81.